[wip] axi request arriving to mem isl, response not received.

pulp-platform · Nov 26, 2024 · e207a28 · e207a28
1 parent e968163
commit e207a28
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Showing 2 changed files with 35 additions and 34 deletions.
diff --git a/Bender.yml b/Bender.yml
@@ -32,7 +32,7 @@ dependencies:
   scm:                    { git: "https://github.com/pulp-platform/scm.git", version: 1.1.0}
   neureka:                { git: "https://github.com/pulp-platform/neureka.git", rev: "8e0883bd0c19c6844122456c749c2bdfde18011f" }
   hci:                    { git: "https://github.com/pulp-platform/hci.git", rev: "df0540ad43ae3b693c040587a50477558f183374" }
-  idma:                   { git: "https://github.com/pulp-platform/idma.git", rev: "ab41a50b2e6dfbfbff9a20537030f6fcfb9cde15" }
+  idma:                   { git: "https://github.com/pulp-platform/idma.git", rev: "d99955ad0883589769ac7a40c5ccc8306ab47090" }
   obi:                    { git: "https://github.com/pulp-platform/obi.git", rev: "2ee698211db5c007bd0d207ebd646ce79f0472ec" }
   register_interface:     { git: "https://github.com/pulp-platform/register_interface.git",  version: 0.4.3  }
   memory_island:          { git: "https://github.com/pulp-platform/memory_island.git", rev: 64828cb7a9ccc1f1656ec92d06129072f445c319 }

diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv
@@ -161,6 +161,7 @@ module pulp_cluster_tb #(
    // Behavioural slaves
    axi_m_req_t  axi_memreq;
    axi_m_resp_t axi_memrsp;
+   axi_m_resp_t axi_simmemrsp;
 
   `AXI_ASSIGN_TO_REQ(axi_memreq, axi_master[1])
   `AXI_ASSIGN_FROM_RESP(axi_master[1], axi_memrsp)
@@ -203,7 +204,7 @@ module pulp_cluster_tb #(
     .axi_req_t  ( dma_axi_req_t ),
     .axi_resp_t ( dma_axi_resp_t ),
     .NoMstPorts ( 2 ),
-    .MaxTrans   ( 16 ), // TODO: Check this value
+    .MaxTrans   ( 2 ), // TODO: Check this value
     .AxiLookBits( DmaAxiDw ),
     .UniqueIds  ( 0 )
     ) i_wide_demux (
@@ -237,8 +238,8 @@ module pulp_cluster_tb #(
     .AddrWidth       ( AxiAw ),
     .NarrowDataWidth ( AxiDw ),
     .WideDataWidth   ( DmaAxiDw ),
-    .AxiNarrowIdWidth( AxiIw ),
-    .AxiWideIdWidth  ( AxiIwMst ),
+    .AxiNarrowIdWidth( AxiIwMst ),
+    .AxiWideIdWidth  ( 1 ),
     .axi_narrow_req_t( axi_m_req_t ),
     .axi_narrow_rsp_t( axi_m_resp_t ),
     .axi_wide_req_t  ( dma_axi_req_t ),
@@ -247,7 +248,7 @@ module pulp_cluster_tb #(
     .NumWideReq      ( 1 ),
     .NumWideBanks    ( 2 ),
     .NarrowExtraBF   ( 1 ),
-    .WordsPerBank    ( 1024 )
+    .WordsPerBank    ( 1024*2 )
   ) i_memory_island (
     .clk_i           ( s_clk ),
     .rst_ni          ( s_rstn ),
@@ -257,35 +258,35 @@ module pulp_cluster_tb #(
     .axi_wide_rsp_o  ( dma_demux_memisl_resp )
   );
 
-  // axi_sim_mem #(
-  //   .AddrWidth ( AxiAw        ),
-  //   .DataWidth ( AxiDw        ),
-  //   .IdWidth   ( AxiIwMst     ),
-  //   .UserWidth ( AxiUw        ),
-  //   .axi_req_t ( axi_m_req_t  ),
-  //   .axi_rsp_t ( axi_m_resp_t ),
-  //   .ApplDelay ( SYS_TA       ),
-  //   .AcqDelay  ( SYS_TT       )
-  // ) sim_mem (
-  //    .clk_i     ( s_clk      ),
-  //    .rst_ni    ( s_rstn     ),
-  //    .axi_req_i ( axi_memreq ),
-  //    .axi_rsp_o ( axi_memrsp ),
-  //    .mon_w_valid_o     (),
-  //    .mon_w_addr_o      (),
-  //    .mon_w_data_o      (),
-  //    .mon_w_id_o        (),
-  //    .mon_w_user_o      (),
-  //    .mon_w_beat_count_o(),
-  //    .mon_w_last_o      (),
-  //    .mon_r_valid_o     (),
-  //    .mon_r_addr_o      (),
-  //    .mon_r_data_o      (),
-  //    .mon_r_id_o        (),
-  //    .mon_r_user_o      (),
-  //    .mon_r_beat_count_o(),
-  //    .mon_r_last_o      ()
-  // );
+  axi_sim_mem #(
+    .AddrWidth ( AxiAw        ),
+    .DataWidth ( AxiDw        ),
+    .IdWidth   ( AxiIwMst     ),
+    .UserWidth ( AxiUw        ),
+    .axi_req_t ( axi_m_req_t  ),
+    .axi_rsp_t ( axi_m_resp_t ),
+    .ApplDelay ( SYS_TA       ),
+    .AcqDelay  ( SYS_TT       )
+  ) sim_mem (
+     .clk_i     ( s_clk      ),
+     .rst_ni    ( s_rstn     ),
+     .axi_req_i ( axi_memreq ),
+     .axi_rsp_o ( axi_simmemrsp ),
+     .mon_w_valid_o     (),
+     .mon_w_addr_o      (),
+     .mon_w_data_o      (),
+     .mon_w_id_o        (),
+     .mon_w_user_o      (),
+     .mon_w_beat_count_o(),
+     .mon_w_last_o      (),
+     .mon_r_valid_o     (),
+     .mon_r_addr_o      (),
+     .mon_r_data_o      (),
+     .mon_r_id_o        (),
+     .mon_r_user_o      (),
+     .mon_r_beat_count_o(),
+     .mon_r_last_o      ()
+  );
 
   mock_uart_axi #(
    .AxiIw   ( AxiIwMst      ),