RISC-V Debug Support v0.4

Added

• Added parameter ReadByteEnable that may be disabled to revert SBA be behavior to 0 on reads
• Optional wrapper dm_obi_top.sv that wraps dm_top providing an OBI compliant interface
• tb that runs dm in conjunction with ri5cy and OpenOCD
• .travis-ci.yml running tb with verilator

Changed

• Made second scratch register optional (default is two) from @zarubaf
• Use latest version of CV32E40P in testbench (#82) @Silabs-ArjanB
• Move assertions into separate module (#82) @Silabs-ArjanB

Fixed

• Fix for SBA be when reading to match the request size from (#70) @jm4rtin
• Off-by-one error in data and progbuf end address from @pbing
• Haltsum1-3 calculation
• A DMI read of SBAddress0 andSBAddress0 will (wrongly) trigger SBBUSYERROR when
  the system bus master is busy (#93) @Silabs-ArjanB
• When the two scratch mode is being used, a0 was loaded instead of saved into
  scratch1 (#90) @Silabs-ArjanB
• dmireset can be accidentally triggered (#89) @Silabs-ArjanB
• enumeration lint issue in ProgBuf (#84) @Silabs-ArjanB
• Fix faulty assertion because of bad hartinfo_i in testbench (#82)
  @Silabs-ArjanB
• Return CmdErrBusy if accessing data or progbuf while command was executing
  (#79) @noytzach