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occamy: Expose tc_sram
configuration inputs per memory type
#303
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Looking good to me! See my readability proposal
lucabertaccini
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…latform/snitch#303) * tc_sram: Add implementation key and IO * vendor: Add `tech_cells_generic` patch * cluster: Add, propagate configurable memory cut configuration ports * doc: Regenerate schema-doc * occamy: Extend wth SRAM config ports at top * occamy: Connect CVA6 SRAM config * occamy: Reorder, count memory config structs * occamy+cluster: Further fixes * cva6: Add SRAM config ports * vendor: Add CVA6 patch * tc_sram: Add implementation stubs to fpga module * vendor: Add `tc_sram` FPGA patch
paulsc96
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…platform/snitch#303](#303s)) * tc_sram: Add implementation key and IO * vendor: Add `tech_cells_generic` patch * cluster: Add, propagate configurable memory cut configuration ports * doc: Regenerate schema-doc * occamy: Extend wth SRAM config ports at top * occamy: Connect CVA6 SRAM config * occamy: Reorder, count memory config structs * occamy+cluster: Further fixes * cva6: Add SRAM config ports * vendor: Add CVA6 patch * tc_sram: Add implementation stubs to fpga module * vendor: Add `tc_sram` FPGA patch
paulsc96
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…latform/snitch#303) * tc_sram: Add implementation key and IO * vendor: Add `tech_cells_generic` patch * cluster: Add, propagate configurable memory cut configuration ports * doc: Regenerate schema-doc * occamy: Extend wth SRAM config ports at top * occamy: Connect CVA6 SRAM config * occamy: Reorder, count memory config structs * occamy+cluster: Further fixes * cva6: Add SRAM config ports * vendor: Add CVA6 patch * tc_sram: Add implementation stubs to fpga module * vendor: Add `tc_sram` FPGA patch
colluca
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…latform/snitch#303) * tc_sram: Add implementation key and IO * vendor: Add `tech_cells_generic` patch * cluster: Add, propagate configurable memory cut configuration ports * doc: Regenerate schema-doc * occamy: Extend wth SRAM config ports at top * occamy: Connect CVA6 SRAM config * occamy: Reorder, count memory config structs * occamy+cluster: Further fixes * cva6: Add SRAM config ports * vendor: Add CVA6 patch * tc_sram: Add implementation stubs to fpga module * vendor: Add `tc_sram` FPGA patch
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Jul 11, 2023
…latform/snitch#303) * tc_sram: Add implementation key and IO * vendor: Add `tech_cells_generic` patch * cluster: Add, propagate configurable memory cut configuration ports * doc: Regenerate schema-doc * occamy: Extend wth SRAM config ports at top * occamy: Connect CVA6 SRAM config * occamy: Reorder, count memory config structs * occamy+cluster: Further fixes * cva6: Add SRAM config ports * vendor: Add CVA6 patch * tc_sram: Add implementation stubs to fpga module * vendor: Add `tc_sram` FPGA patch
paulsc96
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Jul 11, 2023
…latform/snitch#303) * tc_sram: Add implementation key and IO * vendor: Add `tech_cells_generic` patch * cluster: Add, propagate configurable memory cut configuration ports * doc: Regenerate schema-doc * occamy: Extend wth SRAM config ports at top * occamy: Connect CVA6 SRAM config * occamy: Reorder, count memory config structs * occamy+cluster: Further fixes * cva6: Add SRAM config ports * vendor: Add CVA6 patch * tc_sram: Add implementation stubs to fpga module * vendor: Add `tc_sram` FPGA patch
colluca
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Aug 19, 2023
…latform/snitch#303) * tc_sram: Add implementation key and IO * vendor: Add `tech_cells_generic` patch * cluster: Add, propagate configurable memory cut configuration ports * doc: Regenerate schema-doc * occamy: Extend wth SRAM config ports at top * occamy: Connect CVA6 SRAM config * occamy: Reorder, count memory config structs * occamy+cluster: Further fixes * cva6: Add SRAM config ports * vendor: Add CVA6 patch * tc_sram: Add implementation stubs to fpga module * vendor: Add `tc_sram` FPGA patch
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This PR adds quasistatic, parameterizable configuration inputs to all cluster and
occamy_top
SRAMs for implementation purposes. It adopts the interface changes proposed here.For Occamy, the idea is to control these configuration inputs from registers at the chip level. For clusters themselves, they can be enabled or disabled and tied to
'0
if unused in behavioral simulation.