treewide: Miscellaneous changes to bump dependency in Occamy

Bender.lock

@@ -7,8 +7,8 @@ packages:
     dependencies:
     - common_cells
   axi:
-    revision: 4e54ac6766b160217a83a74d5a23af9bbf59e6ee
-    version: null
+    revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7
+    version: 0.39.6
     source:
       Git: https://github.com/pulp-platform/axi
     dependencies:
@@ -50,8 +50,8 @@ packages:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
-    version: 0.2.3
+    revision: fa2630f61666f61d9d78451c4d8b4d1ea403944e
+    version: 0.2.4
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
@@ -71,7 +71,7 @@ packages:
     dependencies:
     - common_cells
   idma:
-    revision: 1a42da9d5c76f1cff0bcdaaacc474ed85631d734
+    revision: d4010425e943c9845b8549b3c8f8cc8dba73ec47
     version: null
     source:
       Git: https://github.com/pulp-platform/iDMA
@@ -91,8 +91,8 @@ packages:
     - common_cells
     - common_verification
   register_interface:
-    revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
-    version: 0.4.4
+    revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467
+    version: 0.4.5
     source:
       Git: https://github.com/pulp-platform/register_interface
     dependencies:

Bender.yml

@@ -19,15 +19,15 @@ package:
     - Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
 
 dependencies:
-  axi:                { git: https://github.com/pulp-platform/axi,                rev:  4e54ac6766b160217a83a74d5a23af9bbf59e6ee  }
+  axi:                { git: https://github.com/pulp-platform/axi,                version:  0.39.6  }
   axi_riscv_atomics:  { git: https://github.com/pulp-platform/axi_riscv_atomics,  version:  0.6.0   }
   common_cells:       { git: https://github.com/pulp-platform/common_cells,       version:  1.35.0  }
   FPnew:              { git: "https://github.com/pulp-platform/cvfpu.git",        rev:      pulp-v0.1.3 }
   register_interface: { git: https://github.com/pulp-platform/register_interface, version:  0.4.2   }
   tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version:  0.2.11  }
   riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg,          version:  0.8.0   }
   cluster_icache:     { git: https://github.com/pulp-platform/cluster_icache.git, version:  0.1.0   }
-  idma:               { git: https://github.com/pulp-platform/iDMA,               rev: __deploy__9cbcd30__snitch-tracing }
+  idma:               { git: https://github.com/pulp-platform/iDMA,               rev: __deploy__110fd06__master }
 
 export_include_dirs:
   - hw/reqrsp_interface/include
@@ -184,9 +184,9 @@ sources:
       - target/common/test/tb_bin.sv
 
   # target/snitch_cluster
-  - target: snitch_cluster
+  - target: snitch_cluster_wrapper
     files:
       - target/snitch_cluster/generated/snitch_cluster_wrapper.sv
-  - target: all(snitch_cluster, any(simulation, verilator))
+  - target: all(snitch_cluster_wrapper, any(simulation, verilator))
     files:
       - target/snitch_cluster/test/testharness.sv

Makefile

@@ -27,7 +27,7 @@ ROOT = $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
 ############
 
 NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/snitch-cluster-nonfree.git
-NONFREE_COMMIT ?= e30961e20a23a76442da27d2ba07c9fe20f3b575
+NONFREE_COMMIT ?= 35cdb5b03778d3ec52e6d8fa0856ee789489b25a
 NONFREE_DIR = $(ROOT)/nonfree
 
 all: nonfree

sw/snRuntime/api/cls_decls.h

@@ -10,6 +10,7 @@
 
 typedef struct {
     uint32_t hw_barrier;
+    uint32_t reduction;
     snrt_allocator_t l1_allocator;
 } cls_t;
 

sw/snRuntime/api/riscv_decls.h

@@ -6,9 +6,9 @@
 
 #include <stdint.h>
 
-static inline void snrt_wfi();
+inline void snrt_wfi();
 
-static inline uint32_t snrt_mcycle();
+inline uint32_t snrt_mcycle();
 
 inline void snrt_interrupt_enable(uint32_t irq);
 

sw/snRuntime/api/sync_decls.h

@@ -28,3 +28,5 @@ inline void snrt_cluster_hw_barrier();
 inline void snrt_global_barrier();
 
 inline uint32_t snrt_global_all_to_all_reduction(uint32_t value);
+
+inline void snrt_wait_writeback(uint32_t val);

sw/snRuntime/src/sync.c

@@ -32,3 +32,5 @@ extern void snrt_global_reduction_dma(double *dst_buffer, double *src_buffer,
                                       size_t len);
 
 extern uint32_t snrt_global_all_to_all_reduction(uint32_t value);
+
+extern void snrt_wait_writeback(uint32_t val);

sw/snRuntime/src/sync.h

@@ -162,9 +162,23 @@ inline void snrt_partial_barrier(snrt_barrier_t *barr, uint32_t n) {
  *       will stall indefinitely.
  */
 inline uint32_t snrt_global_all_to_all_reduction(uint32_t value) {
-    __atomic_add_fetch(&_reduction_result, value, __ATOMIC_RELAXED);
-    snrt_global_barrier();
-    return _reduction_result;
+    // Reduce cores within cluster in TCDM
+    uint32_t *cluster_result = &(cls()->reduction);
+    uint32_t tmp = __atomic_fetch_add(cluster_result, value, __ATOMIC_RELAXED);
+
+    // Wait for writeback to ensure AMO is seen by all cores after barrier
+    snrt_wait_writeback(tmp);
+    snrt_cluster_hw_barrier();
+
+    // Reduce DM cores across clusters in global memory
+    if (snrt_is_dm_core()) {
+        __atomic_add_fetch(&_reduction_result, *cluster_result,
+                           __ATOMIC_RELAXED);
+        snrt_inter_cluster_barrier();
+        *cluster_result = _reduction_result;
+    }
+    snrt_cluster_hw_barrier();
+    return *cluster_result;
 }
 
 /**
@@ -236,3 +250,17 @@ inline void snrt_global_reduction_dma(double *dst_buffer, double *src_buffer,
         }
     }
 }
+
+//================================================================================
+// Memory consistency
+//================================================================================
+
+/**
+ * @brief Ensure value is written back to the register file.
+ * @details This function introduces a RAW dependency on val to stall the
+ *          core until val is written back to the register file.
+ * @param val The variable we want to wait on.
+ */
+inline void snrt_wait_writeback(uint32_t val) {
+    asm volatile("mv %0, %0" : "+r"(val)::);
+}

target/common/common.mk

@@ -12,7 +12,8 @@ UTIL_DIR ?= $(SNITCH_ROOT)/util
 LOGS_DIR  = $(SIM_DIR)/logs
 
 # Files
-BENDER_LOCK ?= $(ROOT)/Bender.lock
+BENDER_LOCK = $(ROOT)/Bender.lock
+BENDER_YML  = $(ROOT)/Bender.yml
 
 # SEPP packages
 QUESTA_SEPP    ?=
@@ -47,15 +48,9 @@ VLT_ROOT        ?= ${VERILATOR_ROOT}
 VLT_JOBS        ?= $(shell nproc)
 VLT_NUM_THREADS ?= 1
 
-MATCH_END := '/+incdir+/ s/$$/\/*\/*/'
-MATCH_BGN := 's/+incdir+//g'
-MATCH_DEF := '/+define+/d'
-SED_SRCS  := sed -e ${MATCH_END} -e ${MATCH_BGN} -e ${MATCH_DEF}
-
-COMMON_BENDER_FLAGS += -t rtl
+COMMON_BENDER_FLAGS += -t rtl -t snitch_cluster
 
 VSIM_BENDER   += $(COMMON_BENDER_FLAGS) -t test -t simulation -t vsim
-VSIM_SOURCES   = $(shell ${BENDER} script flist-plus ${VSIM_BENDER} | ${SED_SRCS})
 VSIM_BUILDDIR ?= work-vsim
 VSIM_FLAGS    += -t 1ps
 ifeq ($(DEBUG), ON)
@@ -68,15 +63,13 @@ endif
 # VCS_BUILDDIR should to be the same as the `DEFAULT : ./work-vcs`
 # in target/snitch_cluster/synopsys_sim.setup
 VCS_BENDER   += $(COMMON_BENDER_FLAGS) -t test -t simulation -t vcs
-VCS_SOURCES   = $(shell ${BENDER} script flist-plus ${VCS_BENDER} | ${SED_SRCS})
 VCS_BUILDDIR := work-vcs
 
 # fesvr is being installed here
 FESVR         ?= ${MKFILE_DIR}work
 FESVR_VERSION ?= 35d50bc40e59ea1d5566fbd3d9226023821b1bb6
 
 VLT_BENDER   += $(COMMON_BENDER_FLAGS) -DCOMMON_CELLS_ASSERTS_OFF
-VLT_SOURCES   = $(shell ${BENDER} script flist-plus ${VLT_BENDER} | ${SED_SRCS})
 VLT_BUILDDIR := $(abspath work-vlt)
 VLT_FESVR     = $(VLT_BUILDDIR)/riscv-isa-sim
 VLT_FLAGS    += --timing
@@ -91,7 +84,7 @@ VLT_FLAGS    += -Wno-UNSIGNED
 VLT_FLAGS    += -Wno-UNOPTFLAT
 VLT_FLAGS    += -Wno-fatal
 VLT_FLAGS    += --unroll-count 1024
-VLT_FLAGS	   += --threads $(VLT_NUM_THREADS)
+VLT_FLAGS    += --threads $(VLT_NUM_THREADS)
 VLT_CFLAGS   += -std=c++20 -pthread
 VLT_CFLAGS   += -I $(VLT_FESVR)/include -I $(TB_DIR) -I ${MKFILE_DIR}test
 
@@ -170,15 +163,6 @@ $(VLT_BUILDDIR)/lib/libfesvr.a: $(VLT_FESVR)/${FESVR_VERSION}_unzip
 	mkdir -p $(dir $@)
 	cp $(dir $<)libfesvr.a $@
 
-#######
-# VCS #
-#######
-$(VCS_BUILDDIR)/compile.sh:
-	mkdir -p $(VCS_BUILDDIR)
-	${BENDER} script vcs ${VCS_BENDER} --vlog-arg="${VLOGAN_FLAGS}" --vcom-arg="${VHDLAN_FLAGS}" > $@
-	chmod +x $@
-	$(VCS_SEPP) $@ > $(VCS_BUILDDIR)/compile.log
-
 ########
 # Util #
 ########

target/common/vcs.mk

@@ -0,0 +1,37 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+VCS_TOP_MODULE = tb_bin
+
+$(VCS_BUILDDIR):
+	mkdir -p $@
+
+$(VCS_BUILDDIR)/compile.sh: $(BENDER_YML) $(BENDER_LOCK) | $(VCS_BUILDDIR)
+	$(BENDER) script vcs $(VCS_BENDER) --vlog-arg="$(VLOGAN_FLAGS)" --vcom-arg="$(VHDLAN_FLAGS)" > $@
+	chmod +x $@
+
+# Generate dependency file with RTL sources and headers using Verilator
+$(VCS_BUILDDIR)/$(VCS_TOP_MODULE).d: $(BENDER_YML) $(BENDER_LOCK) $(GENERATED_RTL_SOURCES) | $(VCS_BUILDDIR)
+	$(VLT) $(shell $(BENDER) script verilator $(VCS_BENDER)) \
+		--Mdir $(VCS_BUILDDIR) --MMD -E --top-module $(VCS_TOP_MODULE) > /dev/null
+	mv $(VCS_BUILDDIR)/V$(VCS_TOP_MODULE)__ver.d $@
+	sed -i 's|^[^:]*:|$(BIN_DIR)/$(TARGET).vcs:|' $@
+
+# Run compilation script and create VCS simulation binary
+$(BIN_DIR)/$(TARGET).vcs: $(VCS_BUILDDIR)/compile.sh $(TB_CC_SOURCES) $(RTL_CC_SOURCES) work/lib/libfesvr.a | $(BIN_DIR)
+	$(VCS_SEPP) $< > $(VCS_BUILDDIR)/compile.log
+	$(VCS) -Mlib=$(VCS_BUILDDIR) -Mdir=$(VCS_BUILDDIR) -o $@ -cc $(CC) -cpp $(CXX) \
+		-assert disable_cover -override_timescale=1ns/1ps -full64 $(VCS_TOP_MODULE) $(TB_CC_SOURCES) $(RTL_CC_SOURCES) \
+		-CFLAGS "$(TB_CC_FLAGS)" -LDFLAGS "-L$(FESVR)/lib" -lfesvr
+
+# Clean all build directories and temporary files for VCS simulation
+.PHONY: clean-vcs
+clean-vcs: clean-work
+	rm -rf $(BIN_DIR)/$(TARGET).vcs $(VCS_BUILDDIR) vc_hdrs.h
+
+clean: clean-vcs
+
+ifneq ($(filter-out clean%,$(MAKECMDGOALS)),)
+-include $(VCS_BUILDDIR)/$(VCS_TOP_MODULE).d
+endif

target/common/verilator.mk

@@ -2,16 +2,29 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-$(BIN_DIR)/$(TARGET).vlt: $(VLT_SOURCES) $(TB_CC_SOURCES) $(VLT_CC_SOURCES) $(VLT_BUILDDIR)/lib/libfesvr.a | $(BIN_DIR)
+VLT_TOP_MODULE = testharness
+
+# Generate dependency file with RTL sources and headers using Verilator
+$(VLT_BUILDDIR)/$(VLT_TOP_MODULE).d: $(BENDER_YML) $(BENDER_LOCK) $(GENERATED_RTL_SOURCES) | $(VLT_BUILDDIR)
+	$(VLT) $(shell $(BENDER) script verilator $(VLT_BENDER)) \
+		--Mdir $(VLT_BUILDDIR) --MMD -E --top-module $(VLT_TOP_MODULE) > /dev/null
+	mv $(VLT_BUILDDIR)/V$(VLT_TOP_MODULE)__ver.d $@
+	sed -i 's|^[^:]*:|$(BIN_DIR)/$(TARGET).vlt:|' $@
+
+$(BIN_DIR)/$(TARGET).vlt: $(TB_CC_SOURCES) $(VLT_CC_SOURCES) $(VLT_BUILDDIR)/lib/libfesvr.a | $(BIN_DIR)
 	$(VLT) $(shell $(BENDER) script verilator $(VLT_BENDER)) \
 		$(VLT_FLAGS) --Mdir $(VLT_BUILDDIR) \
 		-CFLAGS "$(VLT_CFLAGS)" \
 		-LDFLAGS "$(VLT_LDFLAGS)" \
 		-j $(VLT_JOBS) \
-		-o ../$@ --cc --exe --build --top-module testharness $(TB_CC_SOURCES) $(VLT_CC_SOURCES)
+		-o ../$@ --cc --exe --build --top-module $(VLT_TOP_MODULE) $(TB_CC_SOURCES) $(VLT_CC_SOURCES)
 
 .PHONY: clean-vlt
 clean-vlt: clean-work
 	rm -rf $(BIN_DIR)/$(TARGET).vlt $(VLT_BUILDDIR)
 
 clean: clean-vlt
+
+ifneq ($(filter-out clean%,$(MAKECMDGOALS)),)
+-include $(VLT_BUILDDIR)/$(VLT_TOP_MODULE).d
+endif

target/common/vsim.mk

@@ -2,34 +2,47 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
+VSIM_TOP_MODULE = tb_bin
+
 $(VSIM_BUILDDIR):
 	mkdir -p $@
 
-$(VSIM_BUILDDIR)/compile.vsim.tcl: $(BENDER_LOCK) | $(VSIM_BUILDDIR)
+$(VSIM_BUILDDIR)/compile.vsim.tcl: $(BENDER_YML) $(BENDER_LOCK) | $(VSIM_BUILDDIR)
 	$(VLIB) $(dir $@)
 	$(BENDER) script vsim $(VSIM_BENDER) --vlog-arg="$(VLOG_FLAGS) -work $(dir $@) " > $@
 	echo '$(VLOG) -work $(dir $@) $(TB_CC_SOURCES) $(RTL_CC_SOURCES) -vv -ccflags "$(TB_CC_FLAGS)"' >> $@
 	echo 'return 0' >> $@
 
-# Build compilation script and compile all sources for Questasim simulation
-$(BIN_DIR)/$(TARGET).vsim: $(VSIM_BUILDDIR)/compile.vsim.tcl $(VSIM_SOURCES) $(TB_SRCS) $(TB_CC_SOURCES) $(RTL_CC_SOURCES) work/lib/libfesvr.a | $(BIN_DIR)
+# Intermediate file required to avoid "Argument list too long" errors in Occamy
+# when invoking Verilator
+$(VSIM_BUILDDIR)/$(TARGET).f: $(BENDER_YML) $(BENDER_LOCK) | $(VSIM_BUILDDIR)
+	$(BENDER) script verilator $(VSIM_BENDER) > $@
+
+# Generate dependency file with RTL sources and headers using Verilator
+$(VSIM_BUILDDIR)/$(VSIM_TOP_MODULE).d: $(VSIM_BUILDDIR)/$(TARGET).f $(GENERATED_RTL_SOURCES) | $(VSIM_BUILDDIR)
+	$(VLT) -f $< --Mdir $(VSIM_BUILDDIR) --MMD -E --top-module $(VSIM_TOP_MODULE) > /dev/null
+	mv $(VSIM_BUILDDIR)/V$(VSIM_TOP_MODULE)__ver.d $@
+	sed -i 's|^[^:]*:|$(BIN_DIR)/$(TARGET).vsim:|' $@
+
+# Run compilation script and create Questasim simulation binary
+$(BIN_DIR)/$(TARGET).vsim: $(VSIM_BUILDDIR)/compile.vsim.tcl $(TB_CC_SOURCES) $(RTL_CC_SOURCES) work/lib/libfesvr.a | $(BIN_DIR)
 	$(VSIM) -c -do "source $<; quit" | tee $(dir $<)vlog.log
 	@! grep -P "Errors: [1-9]*," $(dir $<)vlog.log
-	$(VOPT) $(VOPT_FLAGS) -work $(VSIM_BUILDDIR) tb_bin -o tb_bin_opt | tee $(dir $<)vopt.log
+	$(VOPT) $(VOPT_FLAGS) -work $(VSIM_BUILDDIR) $(VSIM_TOP_MODULE) -o $(VSIM_TOP_MODULE)_opt | tee $(dir $<)vopt.log
 	@! grep -P "Errors: [1-9]*," $(dir $<)vopt.log
 	@echo "#!/bin/bash" > $@
 	@echo 'binary=$$(realpath $$1)' >> $@
 	@echo 'echo $$binary > .rtlbinary' >> $@
 	@echo '$(VSIM) +permissive $(VSIM_FLAGS) $$3 -work $(MKFILE_DIR)/$(VSIM_BUILDDIR) -c \
 				-ldflags "-Wl,-rpath,$(FESVR)/lib -L$(FESVR)/lib -lfesvr -lutil" \
-				tb_bin_opt +permissive-off ++$$binary ++$$2' >> $@
+				$(VSIM_TOP_MODULE)_opt +permissive-off ++$$binary ++$$2' >> $@
 	@chmod +x $@
 	@echo "#!/bin/bash" > $@.gui
 	@echo 'binary=$$(realpath $$1)' >> $@.gui
 	@echo 'echo $$binary > .rtlbinary' >> $@.gui
 	@echo '$(VSIM) +permissive $(VSIM_FLAGS) -work $(MKFILE_DIR)/$(VSIM_BUILDDIR) \
 				-ldflags "-Wl,-rpath,$(FESVR)/lib -L$(FESVR)/lib -lfesvr -lutil" \
-				tb_bin_opt +permissive-off ++$$binary ++$$2' >> $@.gui
+				$(VSIM_TOP_MODULE)_opt +permissive-off ++$$binary ++$$2' >> $@.gui
 	@chmod +x $@.gui
 
 # Clean all build directories and temporary files for Questasim simulation
@@ -38,3 +51,7 @@ clean-vsim: clean-work
 	rm -rf $(BIN_DIR)/$(TARGET).vsim $(BIN_DIR)/$(TARGET).vsim.gui $(VSIM_BUILDDIR) vsim.wlf
 
 clean: clean-vsim
+
+ifneq ($(filter-out clean%,$(MAKECMDGOALS)),)
+-include $(VSIM_BUILDDIR)/$(VSIM_TOP_MODULE).d
+endif

target/snitch_cluster/Makefile

@@ -66,7 +66,7 @@ $(BIN_DIR):
 # Simulator options #
 #####################
 
-COMMON_BENDER_FLAGS += -t snitch_cluster
+COMMON_BENDER_FLAGS += -t snitch_cluster_wrapper
 
 QUESTA_64BIT = -64
 VLOG_64BIT   = -64
@@ -202,18 +202,7 @@ include $(ROOT)/target/common/vsim.mk
 # VCS #
 #######
 
-.PHONY: clean-vcs
-
-# Clean all build directories and temporary files for VCS simulation
-clean-vcs: clean-work
-	rm -rf $(BIN_DIR)/$(TARGET).vcs $(VCS_BUILDDIR) vc_hdrs.h
-
-# Build compilation script and compile all sources for VCS simulation
-$(BIN_DIR)/$(TARGET).vcs: ${VCS_SOURCES} ${TB_SRCS} $(TB_CC_SOURCES) $(RTL_CC_SOURCES) $(VCS_BUILDDIR)/compile.sh work/lib/libfesvr.a
-	mkdir -p $(BIN_DIR)
-	$(VCS) -Mlib=$(VCS_BUILDDIR) -Mdir=$(VCS_BUILDDIR) -o $(BIN_DIR)/$(TARGET).vcs -cc $(CC) -cpp $(CXX) \
-		-assert disable_cover -override_timescale=1ns/1ps -full64 tb_bin $(TB_CC_SOURCES) $(RTL_CC_SOURCES) \
-		-CFLAGS "$(TB_CC_FLAGS)" -LDFLAGS "-L${FESVR}/lib" -lfesvr
+include $(ROOT)/target/common/vcs.mk
 
 ########
 # Util #