Improve documentation transpiler

src/qililab/digital/circuit_transpiler.py

@@ -68,18 +68,23 @@ def transpile_circuit(
 
         The process involves the following steps:
 
-        1. *)Routing and Placement: Routes and places the circuit's logical qubits onto the chip's physical qubits. The final qubit layout is returned and logged. This step uses the `placer`, `router`, and `routing_iterations` parameters from `transpile_config` if provided; otherwise, default values are applied.
-        2. **)Canceling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ, and SWAPs).
+        1. \\*)Routing and Placement: Routes and places the circuit's logical qubits onto the chip's physical qubits. The final qubit layout is returned and logged. This step uses the ``placer``, ``router``, and ``routing_iterations`` parameters from ``transpile_config`` if provided; otherwise, default values are applied.
+
+        2. \\**)Canceling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ, and SWAPs).
+
         3. Native Gate Translation: Translates the circuit into the chip's native gate set (CZ, RZ, Drag, Wait, and M (Measurement)).
+
         4. Commuting virtual RZ gates and adding phase corrections from CZ.
-        5. **)Optimizing the resulting Drag gates, by combining multiple pulses into a single one.
-        6. Pulse Schedule Conversion: Converts the native gate circuit into a pulse schedule using calibrated settings from the runcard.
+
+        5. \\**)Optimizing the resulting Drag gates, by combining multiple pulses into a single one.
+
+        6. Pulse Schedule Conversion: Converts the native gates into a pulse schedule using calibrated settings from the runcard.
 
         |
 
-        *) If `routing=False` in `transpile_config` (default behavior), step 1. is skipped.
+        \\*) If ``routing=False`` in ``transpile_config`` (default behavior), step 1. is skipped.
 
-        **) If `optimize=False` in `transpile_config` (default behavior), steps 2. and 5. are skipped.
+        \\**) If ``optimize=False`` in ``transpile_config`` (default behavior), steps 2. and 5. are skipped.
 
         The rest of steps are always done.
         |

src/qililab/execute_circuit.py

@@ -34,10 +34,10 @@ def execute(
 
     1. \\*)Routes and places the circuit's logical qubits onto the chip's physical qubits. The final qubit layout is returned and logged.
     2. \\**)Canceling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ, and SWAPs).
-    3. Translates the circuit into the chip's native gate set (CZ, RZ, Drag, Wait, and M (Measurement)).
+    3. Translates the circuit into the chip's native gate set (CZ, RZ, Drag, Wait, and M).
     4. Commuting virtual RZ gates and adding phase corrections from CZ.
     5. \\**)Optimizing the resulting Drag gates, by combining multiple pulses into a single one.
-    6. Converts the native gate circuit into a pulse schedule using calibrated settings from the runcard.
+    6. Converts the native gates into a pulse schedule using calibrated settings from the runcard.
 
     .. note ::
 

src/qililab/platform/platform.py

@@ -997,10 +997,10 @@ def execute(
 
         1. \\*)Routes and places the circuit's logical qubits onto the chip's physical qubits. The final qubit layout is returned and logged.
         2. \\**)Canceling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ, and SWAPs).
-        3. Translates the circuit into the chip's native gate set (CZ, RZ, Drag, Wait, and M (Measurement)).
+        3. Translates the circuit into the chip's native gate set (CZ, RZ, Drag, Wait, and M).
         4. Commuting virtual RZ gates and adding phase corrections from CZ.
         5. \\**)Optimizing the resulting Drag gates, by combining multiple pulses into a single one.
-        6. Converts the native gate circuit into a pulse schedule using calibrated settings from the runcard.
+        6. Converts the native gates into a pulse schedule using calibrated settings from the runcard.
 
         .. note ::
 
@@ -1135,10 +1135,10 @@ def compile(
 
         1. \\*)Routes and places the circuit's logical qubits onto the chip's physical qubits. The final qubit layout is returned and logged.
         2. \\**)Canceling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ, and SWAPs).
-        3. Translates the circuit into the chip's native gate set (CZ, RZ, Drag, Wait, and M (Measurement)).
+        3. Translates the circuit into the chip's native gate set (CZ, RZ, Drag, Wait, and M).
         4. Commuting virtual RZ gates and adding phase corrections from CZ.
         5. \\**)Optimizing the resulting Drag gates, by combining multiple pulses into a single one.
-        6. Converts the native gate circuit into a pulse schedule using calibrated settings from the runcard.
+        6. Converts the native gates into a pulse schedule using calibrated settings from the runcard.
 
         .. note ::