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Hexagon (target/hexagon) Analyze packet for HVX
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Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
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@taylorsimpson
taylorsimpson committed Jan 10, 2023
1 parent 3340e9a commit 92bb4b7
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Showing 4 changed files with 57 additions and 50 deletions.
16 changes: 13 additions & 3 deletions target/hexagon/gen_analyze_funcs.py
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Original file line number Diff line number Diff line change
Expand Up @@ -83,24 +83,34 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "V"):
newv = "EXT_DFL"
if (hex_common.is_new_result(tag)):
newv = "EXT_NEW"
elif (hex_common.is_tmp_result(tag)):
newv = "EXT_TMP"
if (regid in {"dd", "xx"}):
f.write("// const int %s = insn->regno[%d];\n" %\
f.write(" const int %s = insn->regno[%d];\n" %\
(regN, regno))
f.write(" ctx_log_vreg_write_pair(ctx, %s, %s, %s);\n" % \
(regN, newv, predicated))
elif (regid in {"uu", "vv"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"s", "u", "v", "w"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
elif (regid in {"d", "x", "y"}):
f.write("// const int %s = insn->regno[%d];\n" % \
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(" ctx_log_vreg_write(ctx, %s, %s, %s);\n" % \
(regN, newv, predicated))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "Q"):
if (regid in {"d", "e", "x"}):
f.write("// const int %s = insn->regno[%d];\n" % \
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(" ctx_log_qreg_write(ctx, %s);\n" % (regN))
elif (regid in {"s", "t", "u", "v"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
Expand Down
37 changes: 0 additions & 37 deletions target/hexagon/gen_tcg_funcs.py
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Original file line number Diff line number Diff line change
Expand Up @@ -126,26 +126,6 @@ def genptr_decl(f, tag, regtype, regid, regno):
f.write(" ctx_future_vreg_off(ctx, %s%sN," % \
(regtype, regid))
f.write(" 2, true);\n")
if ('A_CONDEXEC' in hex_common.attribdict[tag]):
f.write(" if (!is_vreg_preloaded(ctx, %s)) {\n" % regN)
f.write(" intptr_t src_off =")
f.write(" offsetof(CPUHexagonState, VRegs[%s%sN]);\n"% \
(regtype, regid))
f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
(regtype, regid))
f.write(" src_off,\n")
f.write(" sizeof(MMVector),\n")
f.write(" sizeof(MMVector));\n")
f.write(" src_off = ")
f.write("offsetof(CPUHexagonState, VRegs[%s%sN + 1]);\n" % \
(regtype, regid))
f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off +" % \
(regtype, regid))
f.write(" sizeof(MMVector),\n")
f.write(" src_off,\n")
f.write(" sizeof(MMVector),\n")
f.write(" sizeof(MMVector));\n")
f.write(" }\n")
if (not hex_common.skip_qemu_helper(tag)):
f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
(regtype, regid))
Expand Down Expand Up @@ -187,17 +167,6 @@ def genptr_decl(f, tag, regtype, regid, regno):
f.write(" ctx_future_vreg_off(ctx, %s%sN," % \
(regtype, regid))
f.write(" 1, true);\n");
if ('A_CONDEXEC' in hex_common.attribdict[tag]):
f.write(" if (!is_vreg_preloaded(ctx, %s)) {\n" % (regN))
f.write(" intptr_t src_off =")
f.write(" offsetof(CPUHexagonState, VRegs[%s%sN]);\n"% \
(regtype, regid))
f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
(regtype, regid))
f.write(" src_off,\n")
f.write(" sizeof(MMVector),\n")
f.write(" sizeof(MMVector));\n")
f.write(" }\n")

if (not hex_common.skip_qemu_helper(tag)):
f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
Expand Down Expand Up @@ -659,22 +628,16 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"):
(regtype, regid, regtype, regid))
f.write("%s);\n" % \
(newv))
f.write(" ctx_log_vreg_write_pair(ctx, %s%sN, %s);\n" % \
(regtype, regid, newv))
elif (regid in {"d", "x", "y"}):
f.write(" gen_log_vreg_write(ctx, %s%sV_off, %s%sN, %s);\n" % \
(regtype, regid, regtype, regid, newv))
f.write(" ctx_log_vreg_write(ctx, %s%sN, %s);\n" % \
(regtype, regid, newv))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "Q"):
if (regid in {"d", "e", "x"}):
f.write(" gen_log_qreg_write(%s%sV_off, %s%sN, %s, " % \
(regtype, regid, regtype, regid, newv))
f.write("insn->slot);\n")
f.write(" ctx_log_qreg_write(ctx, %s%sN);\n" % \
(regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
else:
Expand Down
30 changes: 30 additions & 0 deletions target/hexagon/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -373,6 +373,8 @@ static void gen_start_packet(DisasContext *ctx)
bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS);
bitmap_zero(ctx->vregs_updated, NUM_VREGS);
bitmap_zero(ctx->vregs_select, NUM_VREGS);
bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS);
bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS);
ctx->qreg_log_idx = 0;
for (i = 0; i < STORES_MAX; i++) {
ctx->store_width[i] = 0;
Expand Down Expand Up @@ -419,6 +421,34 @@ static void gen_start_packet(DisasContext *ctx)
i + 1);
}
}

/* Preload the HVX registers into future_VRegs and tmp_VRegs */
if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) {
int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
while (i < NUM_VREGS) {
const intptr_t VdV_off =
ctx_future_vreg_off(ctx, i, 1, true);
intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]);
tcg_gen_gvec_mov(MO_64, VdV_off,
src_off,
sizeof(MMVector),
sizeof(MMVector));
i = find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i + 1);
}
}
if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) {
int i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
while (i < NUM_VREGS) {
const intptr_t VdV_off =
ctx_tmp_vreg_off(ctx, i, 1, true);
intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]);
tcg_gen_gvec_mov(MO_64, VdV_off,
src_off,
sizeof(MMVector),
sizeof(MMVector));
i = find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + 1);
}
}
}

bool is_gather_store_insn(DisasContext *ctx)
Expand Down
24 changes: 14 additions & 10 deletions target/hexagon/translate.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,8 @@ typedef struct DisasContext {
DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
DECLARE_BITMAP(vregs_updated, NUM_VREGS);
DECLARE_BITMAP(vregs_select, NUM_VREGS);
DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
int qreg_log[NUM_QREGS];
int qreg_log_idx;
bool pre_commit;
Expand Down Expand Up @@ -96,39 +98,41 @@ static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum,
ctx_log_reg_write(ctx, rnum + 1, is_predicated);
}

static inline bool is_vreg_preloaded(DisasContext *ctx, int num)
{
return test_bit(num, ctx->vregs_updated) ||
test_bit(num, ctx->vregs_updated_tmp);
}

intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
int num, bool alloc_ok);
intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
int num, bool alloc_ok);

static inline void ctx_log_vreg_write(DisasContext *ctx,
int rnum, VRegWriteType type)
int rnum, VRegWriteType type,
bool is_predicated)
{
if (type != EXT_TMP) {
ctx->vreg_log[ctx->vreg_log_idx] = rnum;
ctx->vreg_log_idx++;

set_bit(rnum, ctx->vregs_updated);
if (is_predicated) {
set_bit(rnum, ctx->predicated_future_vregs);
}
}
if (type == EXT_NEW) {
set_bit(rnum, ctx->vregs_select);
}
if (type == EXT_TMP) {
set_bit(rnum, ctx->vregs_updated_tmp);
if (is_predicated) {
set_bit(rnum, ctx->predicated_tmp_vregs);
}
}
}

static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
int rnum, VRegWriteType type)
int rnum, VRegWriteType type,
bool is_predicated)
{
ctx_log_vreg_write(ctx, rnum ^ 0, type);
ctx_log_vreg_write(ctx, rnum ^ 1, type);
ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
}

static inline void ctx_log_qreg_write(DisasContext *ctx, int rnum)
Expand Down

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