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rtl: code refactoring
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@redchenjs
redchenjs committed Jul 12, 2020
1 parent 9823ad6 commit 1abf97b
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Showing 7 changed files with 47 additions and 50 deletions.
8 changes: 4 additions & 4 deletions rtl/layer_code.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,9 @@ module layer_code(
input logic [3:0] wr_byte_en_in,

input logic [7:0] t0h_cnt_in,
input logic [7:0] t0l_cnt_in,
input logic [7:0] t0s_cnt_in,
input logic [7:0] t1h_cnt_in,
input logic [7:0] t1l_cnt_in,
input logic [7:0] t1s_cnt_in,

output logic ws281x_code_out
);
Expand Down Expand Up @@ -67,9 +67,9 @@ ws281x_conf ws281x_conf(
.bit_data_in(bit_data),

.t0h_cnt_in(t0h_cnt_in),
.t0l_cnt_in(t0l_cnt_in),
.t0s_cnt_in(t0s_cnt_in),
.t1h_cnt_in(t1h_cnt_in),
.t1l_cnt_in(t1l_cnt_in),
.t1s_cnt_in(t1s_cnt_in),

.tim_sum_out(tim_sum)
);
Expand Down
8 changes: 4 additions & 4 deletions rtl/layer_conf.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,9 @@ module layer_conf(
input logic [7:0] wr_data_in,

output logic [7:0] t0h_cnt_out,
output logic [7:0] t0l_cnt_out,
output logic [7:0] t0s_cnt_out,
output logic [7:0] t1h_cnt_out,
output logic [7:0] t1l_cnt_out
output logic [7:0] t1s_cnt_out
);

logic [7:0] t0h_cnt;
Expand All @@ -25,9 +25,9 @@ logic [7:0] t1h_cnt;
logic [7:0] t1l_cnt;

assign t0h_cnt_out = t0h_cnt;
assign t0l_cnt_out = t0l_cnt;
assign t0s_cnt_out = t0h_cnt + t0l_cnt;
assign t1h_cnt_out = t1h_cnt;
assign t1l_cnt_out = t1l_cnt;
assign t1s_cnt_out = t1h_cnt + t1l_cnt;

always_ff @(posedge clk_in or negedge rst_n_in)
begin
Expand Down
40 changes: 20 additions & 20 deletions rtl/top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -33,9 +33,9 @@ logic [5:0] wr_addr;
logic [3:0] wr_byte_en;

logic [7:0] t0h_cnt;
logic [7:0] t0l_cnt;
logic [7:0] t0s_cnt;
logic [7:0] t1h_cnt;
logic [7:0] t1l_cnt;
logic [7:0] t1s_cnt;

sys_ctrl sys_ctrl(
.clk_in(clk_in),
Expand Down Expand Up @@ -81,9 +81,9 @@ layer_conf layer_conf(
.wr_data_in(byte_data),

.t0h_cnt_out(t0h_cnt),
.t0l_cnt_out(t0l_cnt),
.t0s_cnt_out(t0s_cnt),
.t1h_cnt_out(t1h_cnt),
.t1l_cnt_out(t1l_cnt)
.t1s_cnt_out(t1s_cnt)
);

layer_code layer_code7(
Expand All @@ -97,9 +97,9 @@ layer_code layer_code7(
.wr_byte_en_in(wr_byte_en),

.t0h_cnt_in(t0h_cnt),
.t0l_cnt_in(t0l_cnt),
.t0s_cnt_in(t0s_cnt),
.t1h_cnt_in(t1h_cnt),
.t1l_cnt_in(t1l_cnt),
.t1s_cnt_in(t1s_cnt),

.ws281x_code_out(ws281x_code_out[7])
);
Expand All @@ -115,9 +115,9 @@ layer_code layer_code6(
.wr_byte_en_in(wr_byte_en),

.t0h_cnt_in(t0h_cnt),
.t0l_cnt_in(t0l_cnt),
.t0s_cnt_in(t0s_cnt),
.t1h_cnt_in(t1h_cnt),
.t1l_cnt_in(t1l_cnt),
.t1s_cnt_in(t1s_cnt),

.ws281x_code_out(ws281x_code_out[6])
);
Expand All @@ -133,9 +133,9 @@ layer_code layer_code5(
.wr_byte_en_in(wr_byte_en),

.t0h_cnt_in(t0h_cnt),
.t0l_cnt_in(t0l_cnt),
.t0s_cnt_in(t0s_cnt),
.t1h_cnt_in(t1h_cnt),
.t1l_cnt_in(t1l_cnt),
.t1s_cnt_in(t1s_cnt),

.ws281x_code_out(ws281x_code_out[5])
);
Expand All @@ -151,9 +151,9 @@ layer_code layer_code4(
.wr_byte_en_in(wr_byte_en),

.t0h_cnt_in(t0h_cnt),
.t0l_cnt_in(t0l_cnt),
.t0s_cnt_in(t0s_cnt),
.t1h_cnt_in(t1h_cnt),
.t1l_cnt_in(t1l_cnt),
.t1s_cnt_in(t1s_cnt),

.ws281x_code_out(ws281x_code_out[4])
);
Expand All @@ -169,9 +169,9 @@ layer_code layer_code3(
.wr_byte_en_in(wr_byte_en),

.t0h_cnt_in(t0h_cnt),
.t0l_cnt_in(t0l_cnt),
.t0s_cnt_in(t0s_cnt),
.t1h_cnt_in(t1h_cnt),
.t1l_cnt_in(t1l_cnt),
.t1s_cnt_in(t1s_cnt),

.ws281x_code_out(ws281x_code_out[3])
);
Expand All @@ -187,9 +187,9 @@ layer_code layer_code2(
.wr_byte_en_in(wr_byte_en),

.t0h_cnt_in(t0h_cnt),
.t0l_cnt_in(t0l_cnt),
.t0s_cnt_in(t0s_cnt),
.t1h_cnt_in(t1h_cnt),
.t1l_cnt_in(t1l_cnt),
.t1s_cnt_in(t1s_cnt),

.ws281x_code_out(ws281x_code_out[2])
);
Expand All @@ -205,9 +205,9 @@ layer_code layer_code1(
.wr_byte_en_in(wr_byte_en),

.t0h_cnt_in(t0h_cnt),
.t0l_cnt_in(t0l_cnt),
.t0s_cnt_in(t0s_cnt),
.t1h_cnt_in(t1h_cnt),
.t1l_cnt_in(t1l_cnt),
.t1s_cnt_in(t1s_cnt),

.ws281x_code_out(ws281x_code_out[1])
);
Expand All @@ -223,9 +223,9 @@ layer_code layer_code0(
.wr_byte_en_in(wr_byte_en),

.t0h_cnt_in(t0h_cnt),
.t0l_cnt_in(t0l_cnt),
.t0s_cnt_in(t0s_cnt),
.t1h_cnt_in(t1h_cnt),
.t1l_cnt_in(t1l_cnt),
.t1s_cnt_in(t1s_cnt),

.ws281x_code_out(ws281x_code_out[0])
);
Expand Down
9 changes: 3 additions & 6 deletions rtl/ws281x_conf.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -13,26 +13,23 @@ module ws281x_conf(
input logic bit_data_in,

input logic [7:0] t0h_cnt_in,
input logic [7:0] t0l_cnt_in,
input logic [7:0] t0s_cnt_in,
input logic [7:0] t1h_cnt_in,
input logic [7:0] t1l_cnt_in,
input logic [7:0] t1s_cnt_in,

output logic [7:0] tim_sum_out
);

logic [7:0] tim_sum;

wire [7:0] t0_sum = t0h_cnt_in + t0l_cnt_in;
wire [7:0] t1_sum = t1h_cnt_in + t1l_cnt_in;

assign tim_sum_out = tim_sum;

always_ff @(posedge clk_in or negedge rst_n_in)
begin
if (!rst_n_in) begin
tim_sum <= 8'h00;
end else begin
tim_sum <= bit_rdy_in ? (bit_data_in ? t1_sum : t0_sum) : tim_sum;
tim_sum <= bit_rdy_in ? (bit_data_in ? t1s_cnt_in : t0s_cnt_in) : tim_sum;
end
end

Expand Down
12 changes: 6 additions & 6 deletions simulation/test_layer_code.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -19,9 +19,9 @@ logic [7:0] wr_data_in;
logic [3:0] wr_byte_en_in;

logic [7:0] t0h_cnt_in;
logic [7:0] t0l_cnt_in;
logic [7:0] t0s_cnt_in;
logic [7:0] t1h_cnt_in;
logic [7:0] t1l_cnt_in;
logic [7:0] t1s_cnt_in;

logic ws281x_code_out;

Expand All @@ -36,9 +36,9 @@ layer_code test_layer_code(
.wr_byte_en_in(wr_byte_en_in),

.t0h_cnt_in(t0h_cnt_in),
.t0l_cnt_in(t0l_cnt_in),
.t0s_cnt_in(t0s_cnt_in),
.t1h_cnt_in(t1h_cnt_in),
.t1l_cnt_in(t1l_cnt_in),
.t1s_cnt_in(t1s_cnt_in),

.ws281x_code_out(ws281x_code_out)
);
Expand All @@ -55,9 +55,9 @@ initial begin

// Unit: 10 ns (2 clk)
t0h_cnt_in <= 8'h01;
t0l_cnt_in <= 8'h7f;
t0s_cnt_in <= 8'h80;
t1h_cnt_in <= 8'h7f;
t1l_cnt_in <= 8'h01;
t1s_cnt_in <= 8'h80;

#2 rst_n_in <= 1'b1;
end
Expand Down
8 changes: 4 additions & 4 deletions simulation/test_layer_conf.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,9 +17,9 @@ logic [5:0] wr_addr_in;
logic [7:0] wr_data_in;

logic [7:0] t0h_cnt_out;
logic [7:0] t0l_cnt_out;
logic [7:0] t0s_cnt_out;
logic [7:0] t1h_cnt_out;
logic [7:0] t1l_cnt_out;
logic [7:0] t1s_cnt_out;

layer_conf test_layer_conf(
.clk_in(clk_in),
Expand All @@ -30,9 +30,9 @@ layer_conf test_layer_conf(
.wr_data_in(wr_data_in),

.t0h_cnt_out(t0h_cnt_out),
.t0l_cnt_out(t0l_cnt_out),
.t0s_cnt_out(t0s_cnt_out),
.t1h_cnt_out(t1h_cnt_out),
.t1l_cnt_out(t1l_cnt_out)
.t1s_cnt_out(t1s_cnt_out)
);

initial begin
Expand Down
12 changes: 6 additions & 6 deletions simulation/test_ws281x_conf.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,9 @@ logic bit_rdy_in;
logic bit_data_in;

logic [7:0] t0h_cnt_in;
logic [7:0] t0l_cnt_in;
logic [7:0] t0s_cnt_in;
logic [7:0] t1h_cnt_in;
logic [7:0] t1l_cnt_in;
logic [7:0] t1s_cnt_in;

logic [7:0] tim_sum_out;

Expand All @@ -30,9 +30,9 @@ ws281x_conf test_ws281x_conf(
.bit_data_in(bit_data_in),

.t0h_cnt_in(t0h_cnt_in),
.t0l_cnt_in(t0l_cnt_in),
.t0s_cnt_in(t0s_cnt_in),
.t1h_cnt_in(t1h_cnt_in),
.t1l_cnt_in(t1l_cnt_in),
.t1s_cnt_in(t1s_cnt_in),

.tim_sum_out(tim_sum_out)
);
Expand All @@ -46,9 +46,9 @@ initial begin

// Unit: 10 ns (2 clk)
t0h_cnt_in <= 8'h01;
t0l_cnt_in <= 8'h7f;
t0s_cnt_in <= 8'h80;
t1h_cnt_in <= 8'hfe;
t1l_cnt_in <= 8'h01;
t1s_cnt_in <= 8'hff;

#2 rst_n_in <= 1'b1;
end
Expand Down

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