ip: update to 20.1

redchenjs · Jul 11, 2020 · 31d9bfd · 31d9bfd
1 parent 4fbfab7
commit 31d9bfd
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Showing 6 changed files with 30 additions and 30 deletions.
diff --git a/ip/clk/globalclk.qsys b/ip/clk/globalclk.qsys
@@ -55,7 +55,7 @@
  <module
  name="altclkctrl_0"
  kind="altclkctrl"
- version="19.1"
+ version="20.1"
  enabled="1"
  autoexport="1">
  <parameter name="CLOCK_TYPE" value="1" />

diff --git a/ip/clk/globalclk.sopcinfo b/ip/clk/globalclk.sopcinfo
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="globalclk" kind="globalclk" version="1.0" fabric="QSYS">
- <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
- <!-- 2020.05.08.07:04:05 -->
+ <!-- Format version 20.1 711 (Future versions may contain additional information.) -->
+ <!-- 2020.07.11.18:44:04 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
  <type>java.lang.Integer</type>
- <value>1588892645</value>
+ <value>1594464244</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
@@ -68,7 +68,7 @@
  <module
  name="altclkctrl_0"
  kind="altclkctrl"
- version="19.1"
+ version="20.1"
  path="altclkctrl_0">
  <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -137,7 +137,7 @@ the requested settings for a module instance. -->
  <visible>true</visible>
  <valid>true</valid>
  </parameter>
- <interface name="altclkctrl_input" kind="conduit_end" version="19.1">
+ <interface name="altclkctrl_input" kind="conduit_end" version="20.1">
  <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -186,7 +186,7 @@ parameters are a RESULT of the module parameters. -->
  <role>inclk</role>
  </port>
  </interface>
- <interface name="altclkctrl_output" kind="conduit_end" version="19.1">
+ <interface name="altclkctrl_output" kind="conduit_end" version="20.1">
  <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -242,16 +242,16 @@ parameters are a RESULT of the module parameters. -->
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IModule</subtype>
  <displayName>ALTCLKCTRL Intel FPGA IP</displayName>
- <version>19.1</version>
+ <version>20.1</version>
  </plugin>
  <plugin>
  <instanceCount>2</instanceCount>
  <name>conduit_end</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
  <displayName>Conduit</displayName>
- <version>19.1</version>
+ <version>20.1</version>
  </plugin>
- <reportVersion>19.1 670</reportVersion>
+ <reportVersion>20.1 711</reportVersion>
  <uniqueIdentifier></uniqueIdentifier>
 </EnsembleReport>
diff --git a/ip/clk/globalclk/synthesis/globalclk.debuginfo b/ip/clk/globalclk/synthesis/globalclk.debuginfo
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport name="globalclk" kind="system" version="19.1" fabric="QSYS">
- <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
- <!-- 2020.05.08.07:04:06 -->
+<EnsembleReport name="globalclk" kind="system" version="20.1" fabric="QSYS">
+ <!-- Format version 20.1 711 (Future versions may contain additional information.) -->
+ <!-- 2020.07.11.18:44:05 -->
  <!-- A collection of modules and connections -->
  <parameter name="clockCrossingAdapter">
  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@@ -53,7 +53,7 @@
  </parameter>
  <parameter name="generationId">
  <type>int</type>
- <value>1588892645</value>
+ <value>1594464244</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>true</visible>
@@ -150,7 +150,7 @@
  <module
  name="altclkctrl_0"
  kind="altclkctrl"
- version="19.1"
+ version="20.1"
  path="altclkctrl_0">
  <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -219,7 +219,7 @@ the requested settings for a module instance. -->
  <visible>true</visible>
  <valid>true</valid>
  </parameter>
- <interface name="altclkctrl_input" kind="conduit_end" version="19.1">
+ <interface name="altclkctrl_input" kind="conduit_end" version="20.1">
  <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -268,7 +268,7 @@ parameters are a RESULT of the module parameters. -->
  <role>inclk</role>
  </port>
  </interface>
- <interface name="altclkctrl_output" kind="conduit_end" version="19.1">
+ <interface name="altclkctrl_output" kind="conduit_end" version="20.1">
  <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -324,16 +324,16 @@ parameters are a RESULT of the module parameters. -->
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IModule</subtype>
  <displayName>ALTCLKCTRL Intel FPGA IP</displayName>
- <version>19.1</version>
+ <version>20.1</version>
  </plugin>
  <plugin>
  <instanceCount>2</instanceCount>
  <name>conduit_end</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
  <displayName>Conduit</displayName>
- <version>19.1</version>
+ <version>20.1</version>
  </plugin>
- <reportVersion>19.1 670</reportVersion>
- <uniqueIdentifier>5CE0C587F67700000171F161BA18</uniqueIdentifier>
+ <reportVersion>20.1 711</reportVersion>
+ <uniqueIdentifier>B8975A199DE2000001733D7995C8</uniqueIdentifier>
 </EnsembleReport>
diff --git a/ip/clk/globalclk/synthesis/globalclk.qip b/ip/clk/globalclk/synthesis/globalclk.qip
@@ -1,8 +1,8 @@
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_NAME "Qsys"
-set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_VERSION "20.1"
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_ENV "Qsys"
 set_global_assignment -library "globalclk" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../globalclk.sopcinfo"]
-set_global_assignment -entity "globalclk" -library "globalclk" -name SLD_INFO "QSYS_NAME globalclk HAS_SOPCINFO 1 GENERATION_ID 1588892645"
+set_global_assignment -entity "globalclk" -library "globalclk" -name SLD_INFO "QSYS_NAME globalclk HAS_SOPCINFO 1 GENERATION_ID 1594464244"
 set_global_assignment -library "globalclk" -name MISC_FILE [file join $::quartus(qip_path) "../globalclk.cmp"]
 set_global_assignment -library "globalclk" -name SLD_FILE [file join $::quartus(qip_path) "globalclk.debuginfo"]
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -15,7 +15,7 @@ set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONEN
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_REPORT_HIERARCHY "On"
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU4ODg5MjY0NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU5NDQ2NDI0NA==::QXV0byBHRU5FUkFUSU9OX0lE"
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMDhTQ00xNTNDOEc=::QXV0byBERVZJQ0U="
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -24,7 +24,7 @@ set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -nam
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_VERSION "MjAuMQ=="
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIEZhbWlseQ=="
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfVFlQRQ==::MQ==::SG93IGRvIHlvdSB3YW50IHRvIHVzZSB0aGUgQUxUQ0xLQ1RSTD8="
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NMT0NLUw==::MQ==::SG93IG1hbnkgY2xvY2sgaW5wdXRzIHdvdWxkIHlvdSBsaWtlPw=="
@@ -35,5 +35,5 @@ set_global_assignment -library "globalclk" -name VERILOG_FILE [file join $::quar
 set_global_assignment -library "globalclk" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/globalclk_altclkctrl_0.v"]
 
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_TOOL_NAME "altclkctrl"
-set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_TOOL_VERSION "20.1"
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_TOOL_ENV "Qsys"
diff --git a/ip/clk/globalclk/synthesis/globalclk.v b/ip/clk/globalclk/synthesis/globalclk.v
@@ -1,6 +1,6 @@
 // globalclk.v
 
-// Generated using ACDS version 19.1 670
+// Generated using ACDS version 20.1 711
 
 `timescale 1 ps / 1 ps
 module globalclk (

diff --git a/ip/clk/globalclk/synthesis/submodules/globalclk_altclkctrl_0.v b/ip/clk/globalclk/synthesis/submodules/globalclk_altclkctrl_0.v
@@ -1,11 +1,11 @@
 //altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="MAX 10" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
-//VERSION_BEGIN 19.1 cbx_altclkbuf 2019:09:22:08:02:34:SJ cbx_cycloneii 2019:09:22:08:02:34:SJ cbx_lpm_add_sub 2019:09:22:08:02:34:SJ cbx_lpm_compare 2019:09:22:08:02:34:SJ cbx_lpm_decode 2019:09:22:08:02:34:SJ cbx_lpm_mux 2019:09:22:08:02:34:SJ cbx_mgl 2019:09:22:09:26:20:SJ cbx_nadder 2019:09:22:08:02:34:SJ cbx_stratix 2019:09:22:08:02:34:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_stratixiii 2019:09:22:08:02:34:SJ cbx_stratixv 2019:09:22:08:02:34:SJ VERSION_END
+//VERSION_BEGIN 20.1 cbx_altclkbuf 2020:06:05:12:04:51:SJ cbx_cycloneii 2020:06:05:12:04:51:SJ cbx_lpm_add_sub 2020:06:05:12:04:51:SJ cbx_lpm_compare 2020:06:05:12:04:51:SJ cbx_lpm_decode 2020:06:05:12:04:51:SJ cbx_lpm_mux 2020:06:05:12:04:51:SJ cbx_mgl 2020:06:05:12:11:10:SJ cbx_nadder 2020:06:05:12:04:51:SJ cbx_stratix 2020:06:05:12:04:51:SJ cbx_stratixii 2020:06:05:12:04:51:SJ cbx_stratixiii 2020:06:05:12:04:51:SJ cbx_stratixv 2020:06:05:12:04:51:SJ VERSION_END
 // synthesis VERILOG_INPUT_VERSION VERILOG_2001
 // altera message_off 10463
 
 
 
-// Copyright (C) 2019 Intel Corporation. All rights reserved.
+// Copyright (C) 2020 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions 
 // and other software and tools, and any partner logic 
 // functions, and any output files from any of the foregoing 
@@ -70,7 +70,7 @@ module globalclk_altclkctrl_0_sub
  inclk_wire = {inclk},
  outclk = wire_clkctrl1_outclk;
 endmodule //globalclk_altclkctrl_0_sub
-//VALID FILE // (C) 2001-2019 Intel Corporation. All rights reserved.
+//VALID FILE // (C) 2001-2020 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation