rtl: code clean up

rtl/edge_detect.sv

@@ -18,7 +18,7 @@ module edge_detect(
 
 logic data_a, data_b;
 
-assign pos_edge_out = data_a & ~data_b;
+assign pos_edge_out = ~data_b & data_a;
 assign neg_edge_out = ~data_a & data_b;
 assign both_edge_out = data_a ^ data_b;
 

rtl/layer_code.sv

@@ -0,0 +1,78 @@
+/*
+ * layer_code.sv
+ *
+ * Created on: 2020-04-06 23:09
+ * Author: Jack Chen <redchenjs@live.com>
+ */
+
+module layer_code(
+ input logic clk_in,
+ input logic rst_n_in,
+
+ input logic wr_en_in,
+ input logic wr_done_in,
+ input logic [5:0] wr_addr_in,
+ input logic [7:0] wr_data_in,
+ input logic [3:0] wr_byte_en_in,
+
+ input logic [ 7:0] t0h_cnt_in,
+ input logic [ 7:0] t0l_cnt_in,
+ input logic [ 7:0] t1h_cnt_in,
+ input logic [ 7:0] t1l_cnt_in,
+ input logic [15:0] rst_cnt_in,
+
+ output logic ws2812_code_out
+);
+
+logic rd_en;
+logic [ 5:0] rd_addr;
+logic [31:0] rd_data;
+
+logic bit_rdy, bit_data, bit_done;
+
+ram64 ram64(
+ .aclr(~rst_n_in),
+ .byteena_a(wr_byte_en_in),
+ .clock(clk_in),
+ .data({wr_data_in, wr_data_in, wr_data_in, wr_data_in}),
+ .rdaddress(rd_addr),
+ .rden(rd_en),
+ .wraddress(wr_addr_in),
+ .wren(wr_en_in),
+ .q(rd_data)
+);
+
+ws2812_ctrl ws2812_ctrl(
+ .clk_in(clk_in),
+ .rst_n_in(rst_n_in),
+
+ .bit_done_in(bit_done),
+
+ .wr_done_in(wr_done_in),
+ .rd_data_in(rd_data),
+ .rst_cnt_in(rst_cnt_in),
+
+ .bit_rdy_out(bit_rdy),
+ .bit_data_out(bit_data),
+
+ .rd_en_out(rd_en),
+ .rd_addr_out(rd_addr)
+);
+
+ws2812_code ws2812_code(
+ .clk_in(clk_in),
+ .rst_n_in(rst_n_in),
+
+ .bit_rdy_in(bit_rdy),
+ .bit_data_in(bit_data),
+
+ .t0h_cnt_in(t0h_cnt_in),
+ .t0l_cnt_in(t0l_cnt_in),
+ .t1h_cnt_in(t1h_cnt_in),
+ .t1l_cnt_in(t1l_cnt_in),
+
+ .bit_done_out(bit_done),
+ .bit_code_out(ws2812_code_out)
+);
+
+endmodule

rtl/layer_conf.sv

@@ -0,0 +1,63 @@
+/*
+ * layer_conf.sv
+ *
+ * Created on: 2020-04-29 20:16
+ * Author: Jack Chen <redchenjs@live.com>
+ */
+
+module layer_conf(
+ input logic clk_in,
+ input logic rst_n_in,
+
+ input logic wr_en_in,
+ input logic [5:0] wr_addr_in,
+ input logic [7:0] wr_data_in,
+
+ output logic [ 7:0] t0h_cnt_out,
+ output logic [ 7:0] t0l_cnt_out,
+ output logic [ 7:0] t1h_cnt_out,
+ output logic [ 7:0] t1l_cnt_out,
+ output logic [15:0] rst_cnt_out
+);
+
+logic [ 7:0] t0h_cnt;
+logic [ 7:0] t0l_cnt;
+logic [ 7:0] t1h_cnt;
+logic [ 7:0] t1l_cnt;
+logic [15:0] rst_cnt;
+
+assign t0h_cnt_out = t0h_cnt;
+assign t0l_cnt_out = t0l_cnt;
+assign t1h_cnt_out = t1h_cnt;
+assign t1l_cnt_out = t1l_cnt;
+assign rst_cnt_out = rst_cnt;
+
+always_ff @(posedge clk_in or negedge rst_n_in)
+begin
+ if (!rst_n_in) begin
+ t0h_cnt <= 8'h00;
+ t0l_cnt <= 8'h00;
+ t1h_cnt <= 8'h00;
+ t1l_cnt <= 8'h00;
+ rst_cnt <= 16'h0000;
+ end else begin
+ if (wr_en_in) begin
+ case (wr_addr_in[2:0])
+ 3'h0:
+ t0h_cnt <= wr_data_in;
+ 3'h1:
+ t0l_cnt <= wr_data_in;
+ 3'h2:
+ t1h_cnt <= wr_data_in;
+ 3'h3:
+ t1l_cnt <= wr_data_in;
+ 3'h4:
+ rst_cnt[15:8] <= wr_data_in;
+ 3'h5:
+ rst_cnt[ 7:0] <= wr_data_in;
+ endcase
+ end
+ end
+end
+
+endmodule

rtl/layer_ctl.sv → rtl/layer_ctrl.sv

@@ -1,21 +1,21 @@
 /*
- * layer_ctl.sv
+ * layer_ctrl.sv
  *
  * Created on: 2020-04-06 23:08
  * Author: Jack Chen <redchenjs@live.com>
  */
 
-module layer_ctl(
+module layer_ctrl(
  input logic clk_in,
  input logic rst_n_in,
 
  input logic dc_in,
 
- input logic byte_rdy_in,
+ input logic  byte_rdy_in,
  input logic [7:0] byte_data_in,
 
- output logic wr_done_out,
  output logic [8:0] wr_en_out,
+ output logic wr_done_out,
  output logic [5:0] wr_addr_out,
  output logic [3:0] wr_byte_en_out
 );
@@ -24,88 +24,91 @@ parameter [7:0] CUBE0414_CONF_WR = 8'h2a;
 parameter [7:0] CUBE0414_ADDR_WR = 8'h2b;
 parameter [7:0] CUBE0414_DATA_WR = 8'h2c;
 
-logic conf_wr;
-logic [7:0] data_wr;
+logic  conf_wr;
+logic [7:0] code_wr;
 
-logic addr_en;
-logic [2:0] color_en;
+logic  addr_en;
+logic [2:0] data_en;
 
-wire conf_done = (wr_addr_out == 6'd5);
-wire data_done = data_wr[0];
+logic [5:0] wr_addr;
 
-wire addr_done = (wr_addr_out == 6'd63);
-wire color_done = color_en[0];
+wire conf_done = (wr_addr == 6'd5);
+wire code_done = code_wr[0];
 
-wire layer_done = addr_done & color_done;
-wire frame_done = data_done & layer_done;
+wire addr_done = (wr_addr == 6'd63);
+wire data_done = data_en[0];
 
-assign wr_done_out = byte_rdy_in & frame_done;
+wire layer_done = addr_done & data_done;
+wire frame_done = code_done & layer_done;
 
 assign wr_en_out[8] = byte_rdy_in & conf_wr;
-assign wr_en_out[7] = byte_rdy_in & data_wr[7];
-assign wr_en_out[6] = byte_rdy_in & data_wr[6];
-assign wr_en_out[5] = byte_rdy_in & data_wr[5];
-assign wr_en_out[4] = byte_rdy_in & data_wr[4];
-assign wr_en_out[3] = byte_rdy_in & data_wr[3];
-assign wr_en_out[2] = byte_rdy_in & data_wr[2];
-assign wr_en_out[1] = byte_rdy_in & data_wr[1];
-assign wr_en_out[0] = byte_rdy_in & data_wr[0];
+assign wr_en_out[7] = byte_rdy_in & code_wr[7];
+assign wr_en_out[6] = byte_rdy_in & code_wr[6];
+assign wr_en_out[5] = byte_rdy_in & code_wr[5];
+assign wr_en_out[4] = byte_rdy_in & code_wr[4];
+assign wr_en_out[3] = byte_rdy_in & code_wr[3];
+assign wr_en_out[2] = byte_rdy_in & code_wr[2];
+assign wr_en_out[1] = byte_rdy_in & code_wr[1];
+assign wr_en_out[0] = byte_rdy_in & code_wr[0];
+
+assign wr_done_out = byte_rdy_in & frame_done;
+assign wr_addr_out = wr_addr;
 
-assign wr_byte_en_out = {addr_en, color_en};
+assign wr_byte_en_out = {addr_en, data_en};
 
 always_ff @(posedge clk_in or negedge rst_n_in)
 begin
  if (!rst_n_in) begin
  conf_wr <= 1'b0;
- data_wr <= 8'h00;
+ code_wr <= 8'h00;
 
  addr_en <= 1'b0;
- color_en <= 3'b000;
+ data_en <= 3'b000;
 
- wr_addr_out <= 6'h00;
+ wr_addr <= 6'h00;
  end else begin
  if (byte_rdy_in) begin
  if (!dc_in) begin // Command
  case (byte_data_in)
  CUBE0414_CONF_WR: begin // Write Reg Conf
  conf_wr <= 1'b1;
- data_wr <= 8'h00;
+ code_wr <= 8'h00;
 
  addr_en <= 1'b0;
- color_en <= 3'b000;
+ data_en <= 3'b000;
  end
  CUBE0414_ADDR_WR: begin // Write RAM Addr
  conf_wr <= 1'b0;
- data_wr <= 8'hff;
+ code_wr <= 8'hff;
 
  addr_en <= 1'b1;
- color_en <= 3'b000;
+ data_en <= 3'b000;
  end
  CUBE0414_DATA_WR: begin // Write RAM Data
  conf_wr <= 1'b0;
- data_wr <= 8'h80;
+ code_wr <= 8'h80;
 
  addr_en <= 1'b0;
- color_en <= 3'b100;
+ data_en <= 3'b100;
  end
  default: begin
  conf_wr <= 1'b0;
- data_wr <= 8'h00;
+ code_wr <= 8'h00;
 
  addr_en <= 1'b0;
- color_en <= 3'b000;
+ data_en <= 3'b000;
  end
  endcase
 
- wr_addr_out <= 6'h00;
+ wr_addr <= 6'h00;
  end else begin // Data
  conf_wr <= conf_wr & ~conf_done;
- data_wr <= data_wr >> (~(conf_wr | addr_en) & layer_done);
+ code_wr <= code_wr >> (~(conf_wr | addr_en) & layer_done);
 
  addr_en <= addr_en & ~addr_done;
- color_en <= {color_en[0], color_en[2:1]};
+ data_en <= {data_en[0], data_en[2:1]};
 
- wr_addr_out <= wr_addr_out + (conf_wr | addr_en | color_done);
+ wr_addr <= wr_addr + (conf_wr | addr_en | data_done);
  end
  end
  end