rtl: update SYNC_BIT timing

rtl/layer_code.sv

@@ -26,6 +26,7 @@ module layer_code(
 logic rd_en;
 logic [ 5:0] rd_addr;
 logic [31:0] rd_data;
+logic [ 7:0] tim_sum;
 
 logic bit_rdy, bit_data, bit_done;
 
@@ -49,6 +50,7 @@ ws281x_ctrl ws281x_ctrl(
 
  .wr_done_in(wr_done_in),
  .rd_data_in(rd_data),
+ .tim_sum_in(tim_sum),
 
  .bit_rdy_out(bit_rdy),
  .bit_data_out(bit_data),
@@ -57,7 +59,7 @@ ws281x_ctrl ws281x_ctrl(
  .rd_addr_out(rd_addr)
 );
 
-ws281x_code ws281x_code(
+ws281x_conf ws281x_conf(
  .clk_in(clk_in),
  .rst_n_in(rst_n_in),
 
@@ -69,6 +71,20 @@ ws281x_code ws281x_code(
  .t1h_cnt_in(t1h_cnt_in),
  .t1l_cnt_in(t1l_cnt_in),
 
+ .tim_sum_out(tim_sum)
+);
+
+ws281x_code ws281x_code(
+ .clk_in(clk_in),
+ .rst_n_in(rst_n_in),
+
+ .bit_rdy_in(bit_rdy),
+ .bit_data_in(bit_data),
+
+ .t0h_cnt_in(t0h_cnt_in),
+ .t1h_cnt_in(t1h_cnt_in),
+ .tim_sum_in(tim_sum),
+
  .bit_done_out(bit_done),
  .bit_code_out(ws281x_code_out)
 );

rtl/ws281x_code.sv

@@ -13,25 +13,19 @@ module ws281x_code(
  input logic bit_data_in,
 
  input logic [7:0] t0h_cnt_in,
- input logic [7:0] t0l_cnt_in,
  input logic [7:0] t1h_cnt_in,
- input logic [7:0] t1l_cnt_in,
+ input logic [7:0] tim_sum_in,
 
  output logic bit_done_out,
  output logic bit_code_out
 );
 
-logic [7:0] cnt_sum;
-
 logic bit_bsy;
 logic [8:0] bit_cnt;
 
 logic bit_done, bit_code;
 
-wire [7:0] t0_sum = t0h_cnt_in + t0l_cnt_in;
-wire [7:0] t1_sum = t1h_cnt_in + t1l_cnt_in;
-
-wire cnt_done = (bit_cnt[8:0] == {cnt_sum, 1'b0} - 2'b11);
+wire cnt_done = (bit_cnt[8:0] == {tim_sum_in, 1'b0} - 2'b11);
 
 wire t0h_time = (bit_cnt[8:1] < t0h_cnt_in);
 wire t1h_time = (bit_cnt[8:1] < t1h_cnt_in);
@@ -42,16 +36,12 @@ assign bit_code_out = bit_code;
 always_ff @(posedge clk_in or negedge rst_n_in)
 begin
  if (!rst_n_in) begin
- cnt_sum <= 8'h00;
-
  bit_bsy <= 1'b0;
  bit_cnt <= 9'h000;
 
  bit_done <= 1'b0;
  bit_code <= 1'b0;
  end else begin
- cnt_sum <= bit_rdy_in ? (bit_data_in ? t1_sum : t0_sum) : cnt_sum;
-
  bit_bsy <= bit_bsy ? ~cnt_done : bit_rdy_in;
  bit_cnt <= bit_bsy ? bit_cnt + 1'b1 : 9'h000;
 

rtl/ws281x_conf.sv

@@ -0,0 +1,39 @@
+/*
+ * ws281x_conf.sv
+ *
+ * Created on: 2020-07-10 14:29
+ * Author: Jack Chen <redchenjs@live.com>
+ */
+
+module ws281x_conf(
+ input logic clk_in,
+ input logic rst_n_in,
+
+ input logic bit_rdy_in,
+ input logic bit_data_in,
+
+ input logic [7:0] t0h_cnt_in,
+ input logic [7:0] t0l_cnt_in,
+ input logic [7:0] t1h_cnt_in,
+ input logic [7:0] t1l_cnt_in,
+
+ output logic [7:0] tim_sum_out
+);
+
+logic [7:0] tim_sum;
+
+wire [7:0] t0_sum = t0h_cnt_in + t0l_cnt_in;
+wire [7:0] t1_sum = t1h_cnt_in + t1l_cnt_in;
+
+assign tim_sum_out = tim_sum;
+
+always_ff @(posedge clk_in or negedge rst_n_in)
+begin
+ if (!rst_n_in) begin
+ tim_sum <= 8'h00;
+ end else begin
+ tim_sum <= bit_rdy_in ? (bit_data_in ? t1_sum : t0_sum) : tim_sum;
+ end
+end
+
+endmodule

rtl/ws281x_ctrl.sv

@@ -13,6 +13,7 @@ module ws281x_ctrl(
 
  input logic wr_done_in,
  input logic [31:0] rd_data_in,
+ input logic [ 7:0] tim_sum_in,
 
  output logic bit_rdy_out,
  output logic bit_data_out,
@@ -30,7 +31,7 @@ logic [1:0] ctl_sta;
 
 logic bit_st;
 logic [4:0] bit_sel;
-logic [8:0] bit_syn;
+logic [8:0] bit_cnt;
 
 logic bit_rdy, bit_data;
 
@@ -42,7 +43,7 @@ wire ram_next = (bit_sel == 5'd23);
 wire ram_done = (rd_addr == 6'h00);
 
 wire bit_next = bit_st | bit_done_in;
-wire syn_done = (bit_syn[8:1] == 8'hfe);
+wire cnt_done = (bit_cnt[8:0] == {tim_sum_in, 1'b0} - 3'b110);
 
 assign bit_rdy_out = bit_rdy;
 assign bit_data_out = bit_data;
@@ -73,14 +74,14 @@ begin
  SEND_BIT:
  ctl_sta <= (bit_next & ram_next) ? (ram_done ? SYNC_BIT : READ_RAM) : ctl_sta;
  SYNC_BIT:
- ctl_sta <= syn_done ? IDLE : ctl_sta;
+ ctl_sta <= cnt_done ? IDLE : ctl_sta;
  default:
  ctl_sta <= IDLE;
  endcase
 
  bit_st <= (ctl_sta != SEND_BIT) & ((ctl_sta == IDLE) | bit_st);
  bit_sel <= (ctl_sta == SEND_BIT) ? bit_sel + bit_next : 5'h00;
- bit_syn <= (ctl_sta == SYNC_BIT) ? bit_syn + 1'b1 : 9'h000;
+ bit_cnt <= (ctl_sta == SYNC_BIT) ? bit_cnt + 1'b1 : 9'h000;
 
  bit_rdy <= (ctl_sta == SEND_BIT) & bit_next;
  bit_data <= (ctl_sta == SEND_BIT) & bit_next ? rd_data[5'd23 - bit_sel] : bit_data;

simulation/test_layer_code.sv

@@ -89,12 +89,12 @@ always begin
  wr_en_in <= 1'b1;
  #5 wr_en_in <= 1'b0;
 
- #10 wr_done_in  <= 1'b1;
- #5 wr_done_in  <= 1'b0;
+ #10 wr_done_in <= 1'b1;
+ #5 wr_done_in <= 1'b0;
 
  for (integer i=0; i<65536; i++) begin
- #5 wr_done_in  <= 1'b1;
- #5 wr_done_in  <= 1'b0;
+ #5 wr_done_in <= 1'b1;
+ #5 wr_done_in <= 1'b0;
  end
 
  #75 rst_n_in <= 1'b0;

simulation/test_ws281x_code.sv

@@ -16,9 +16,8 @@ logic bit_rdy_in;
 logic bit_data_in;
 
 logic [7:0] t0h_cnt_in;
-logic [7:0] t0l_cnt_in;
 logic [7:0] t1h_cnt_in;
-logic [7:0] t1l_cnt_in;
+logic [7:0] tim_sum_in;
 
 logic bit_done_out;
 logic bit_code_out;
@@ -31,9 +30,8 @@ ws281x_code test_ws281x_code(
  .bit_data_in(bit_data_in),
 
  .t0h_cnt_in(t0h_cnt_in),
- .t0l_cnt_in(t0l_cnt_in),
  .t1h_cnt_in(t1h_cnt_in),
- .t1l_cnt_in(t1l_cnt_in),
+ .tim_sum_in(tim_sum_in),
 
  .bit_done_out(bit_done_out),
  .bit_code_out(bit_code_out)
@@ -48,9 +46,8 @@ initial begin
 
  // Unit: 10 ns (2 clk)
  t0h_cnt_in <= 8'h01;
- t0l_cnt_in <= 8'h02;
  t1h_cnt_in <= 8'h02;
- t1l_cnt_in <= 8'h01;
+ tim_sum_in <= 8'h03;
 
  #2 rst_n_in <= 1'b1;
 end
@@ -64,9 +61,11 @@ always begin
  bit_data_in <= 1'b0;
  #5 bit_rdy_in <= 1'b0;
 
- #50 bit_rdy_in <= 1'b1;
- bit_data_in <= 1'b1;
- #5 bit_rdy_in <= 1'b0;
+ for (integer i=0; i<10; i++) begin
+ #25 bit_rdy_in <= 1'b1;
+ bit_data_in <= i % 2;
+ #5 bit_rdy_in <= 1'b0;
+ end
 
  #75 rst_n_in <= 1'b0;
  #25 $stop;

simulation/test_ws281x_conf.sv

@@ -0,0 +1,73 @@
+/*
+ * test_ws281x_conf.sv
+ *
+ * Created on: 2020-07-10 14:31
+ * Author: Jack Chen <redchenjs@live.com>
+ */
+
+`timescale 1ns / 1ps
+
+module test_ws281x_conf;
+
+logic clk_in;
+logic rst_n_in;
+
+logic bit_rdy_in;
+logic bit_data_in;
+
+logic [7:0] t0h_cnt_in;
+logic [7:0] t0l_cnt_in;
+logic [7:0] t1h_cnt_in;
+logic [7:0] t1l_cnt_in;
+
+logic [7:0] tim_sum_out;
+
+ws281x_conf test_ws281x_conf(
+ .clk_in(clk_in),
+ .rst_n_in(rst_n_in),
+
+ .bit_rdy_in(bit_rdy_in),
+ .bit_data_in(bit_data_in),
+
+ .t0h_cnt_in(t0h_cnt_in),
+ .t0l_cnt_in(t0l_cnt_in),
+ .t1h_cnt_in(t1h_cnt_in),
+ .t1l_cnt_in(t1l_cnt_in),
+
+ .tim_sum_out(tim_sum_out)
+);
+
+initial begin
+ clk_in <= 1'b1;
+ rst_n_in <= 1'b0;
+
+ bit_rdy_in <= 1'b0;
+ bit_data_in <= 1'b0;
+
+ // Unit: 10 ns (2 clk)
+ t0h_cnt_in <= 8'h01;
+ t0l_cnt_in <= 8'h7f;
+ t1h_cnt_in <= 8'hfe;
+ t1l_cnt_in <= 8'h01;
+
+ #2 rst_n_in <= 1'b1;
+end
+
+always begin
+ #2.5 clk_in <= ~clk_in;
+end
+
+always begin
+ #11 bit_rdy_in <= 1'b1;
+ #5 bit_rdy_in <= 1'b0;
+
+ #10 bit_data_in <= 1'b1;
+
+ #10 bit_rdy_in <= 1'b1;
+ #5 bit_rdy_in <= 1'b0;
+
+ #75 rst_n_in <= 1'b0;
+ #25 $stop;
+end
+
+endmodule

simulation/test_ws281x_ctrl.sv

@@ -16,6 +16,7 @@ logic bit_done_in;
 
 logic wr_done_in;
 logic [31:0] rd_data_in;
+logic [ 7:0] tim_sum_in;
 
 logic bit_rdy_out;
 logic bit_data_out;
@@ -31,6 +32,7 @@ ws281x_ctrl test_ws281x_ctrl(
 
  .wr_done_in(wr_done_in),
  .rd_data_in(rd_data_in),
+ .tim_sum_in(tim_sum_in),
 
  .bit_rdy_out(bit_rdy_out),
  .bit_data_out(bit_data_out),
@@ -46,7 +48,8 @@ initial begin
  bit_done_in <= 1'b0;
 
  wr_done_in <= 1'b0;
- rd_data_in <= 32'haaaa_aaaa;
+ rd_data_in <= 32'haaaa_cccc;
+ tim_sum_in <= 8'h04;
 
  #2 rst_n_in <= 1'b1;
 end
@@ -59,7 +62,14 @@ always begin
  #11 wr_done_in <= 1'b1;
  #5 wr_done_in <= 1'b0;
 
- for (integer i=0; i<1536; i++) begin
+ for (integer i=0; i<119; i++) begin
+ #50 bit_done_in <= 1'b1;
+ #5 bit_done_in <= 1'b0;
+ end
+
+ #500 rd_data_in <= 32'h00aa_dddd;
+
+ for (integer i=0; i<119; i++) begin
  #50 bit_done_in <= 1'b1;
  #5 bit_done_in <= 1'b0;
  end

ws281x_cube_controller.qsf

@@ -19,7 +19,7 @@
 #
 # Quartus Prime
 # Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
-# Date created = 10:37:22 July 09, 2020
+# Date created = 16:06:46 July 10, 2020
 #
 # -------------------------------------------------------------------------- #
 #
@@ -54,6 +54,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/layer_ctrl.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/layer_conf.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/layer_code.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/ws281x_ctrl.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/ws281x_conf.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/ws281x_code.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/segment_led.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/pulse_counter.sv
@@ -233,6 +234,18 @@ set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM
 # end EDA_TEST_BENCH_SETTINGS(test_ws281x_ctrl)
 # ---------------------------------------------
 
+# start EDA_TEST_BENCH_SETTINGS(test_ws281x_conf)
+# -----------------------------------------------
+
+ # EDA Netlist Writer Assignments
+ # ==============================
+ set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_ws281x_conf
+ set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_ws281x_conf -section_id test_ws281x_conf
+ set_global_assignment -name EDA_TEST_BENCH_FILE simulation/test_ws281x_conf.sv -section_id test_ws281x_conf
+
+# end EDA_TEST_BENCH_SETTINGS(test_ws281x_conf)
+# ---------------------------------------------
+
 # start EDA_TEST_BENCH_SETTINGS(test_ws281x_code)
 # -----------------------------------------------
 
@@ -261,6 +274,7 @@ set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM
  set_global_assignment -name EDA_TEST_BENCH_NAME test_layer_conf -section_id eda_simulation
  set_global_assignment -name EDA_TEST_BENCH_NAME test_layer_code -section_id eda_simulation
  set_global_assignment -name EDA_TEST_BENCH_NAME test_ws281x_ctrl -section_id eda_simulation
+ set_global_assignment -name EDA_TEST_BENCH_NAME test_ws281x_conf -section_id eda_simulation
  set_global_assignment -name EDA_TEST_BENCH_NAME test_ws281x_code -section_id eda_simulation
 
 # end EDA_TOOL_SETTINGS(eda_simulation)