ip/clk: remove unused ena port

redchenjs · May 7, 2020 · bda8b87 · bda8b87
1 parent e1b593d
commit bda8b87
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Showing 8 changed files with 20 additions and 45 deletions.
diff --git a/ip/clk/globalclk.qsys b/ip/clk/globalclk.qsys
@@ -44,7 +44,6 @@
  type="conduit"
  dir="end">
  <port name="inclk" internal="inclk" />
- <port name="ena" internal="ena" />
  </interface>
  <interface
  name="altclkctrl_output"
@@ -62,7 +61,7 @@
  <parameter name="CLOCK_TYPE" value="1" />
  <parameter name="DEVICE_FAMILY" value="MAX 10" />
  <parameter name="ENA_REGISTER_MODE" value="1" />
- <parameter name="GUI_USE_ENA" value="true" />
+ <parameter name="GUI_USE_ENA" value="false" />
  <parameter name="NUMBER_OF_CLOCKS" value="1" />
  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
  </module>

diff --git a/ip/clk/globalclk.sopcinfo b/ip/clk/globalclk.sopcinfo
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="globalclk" kind="globalclk" version="1.0" fabric="QSYS">
  <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
- <!-- 2020.04.09.22:56:32 -->
+ <!-- 2020.05.08.07:04:05 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
  <type>java.lang.Integer</type>
- <value>1586444192</value>
+ <value>1588892645</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
@@ -107,7 +107,7 @@ the requested settings for a module instance. -->
  </parameter>
  <parameter name="GUI_USE_ENA">
  <type>boolean</type>
- <value>true</value>
+ <value>false</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>true</visible>
@@ -185,12 +185,6 @@ parameters are a RESULT of the module parameters. -->
  <width>1</width>
  <role>inclk</role>
  </port>
- <port>
- <name>ena</name>
- <direction>Input</direction>
- <width>1</width>
- <role>ena</role>
- </port>
  </interface>
  <interface name="altclkctrl_output" kind="conduit_end" version="19.1">
  <!-- The connection points exposed by a module instance for the

diff --git a/ip/clk/globalclk/globalclk.cmp b/ip/clk/globalclk/globalclk.cmp
@@ -1,7 +1,6 @@
  component globalclk is
  port (
  inclk : in std_logic := 'X'; -- inclk
- ena : in std_logic := 'X'; -- ena
  outclk : out std_logic -- outclk
  );
  end component globalclk;

diff --git a/ip/clk/globalclk/synthesis/globalclk.debuginfo b/ip/clk/globalclk/synthesis/globalclk.debuginfo
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="globalclk" kind="system" version="19.1" fabric="QSYS">
  <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
- <!-- 2020.04.09.22:56:33 -->
+ <!-- 2020.05.08.07:04:06 -->
  <!-- A collection of modules and connections -->
  <parameter name="clockCrossingAdapter">
  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@@ -53,7 +53,7 @@
  </parameter>
  <parameter name="generationId">
  <type>int</type>
- <value>1586444192</value>
+ <value>1588892645</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>true</visible>
@@ -189,7 +189,7 @@ the requested settings for a module instance. -->
  </parameter>
  <parameter name="GUI_USE_ENA">
  <type>boolean</type>
- <value>true</value>
+ <value>false</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>true</visible>
@@ -267,12 +267,6 @@ parameters are a RESULT of the module parameters. -->
  <width>1</width>
  <role>inclk</role>
  </port>
- <port>
- <name>ena</name>
- <direction>Input</direction>
- <width>1</width>
- <role>ena</role>
- </port>
  </interface>
  <interface name="altclkctrl_output" kind="conduit_end" version="19.1">
  <!-- The connection points exposed by a module instance for the
@@ -341,5 +335,5 @@ parameters are a RESULT of the module parameters. -->
  <version>19.1</version>
  </plugin>
  <reportVersion>19.1 670</reportVersion>
- <uniqueIdentifier>005056C00008000001715F714CC9</uniqueIdentifier>
+ <uniqueIdentifier>5CE0C587F67700000171F161BA18</uniqueIdentifier>
 </EnsembleReport>
diff --git a/ip/clk/globalclk/synthesis/globalclk.qip b/ip/clk/globalclk/synthesis/globalclk.qip
@@ -2,7 +2,7 @@ set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_NAM
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_VERSION "19.1"
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_ENV "Qsys"
 set_global_assignment -library "globalclk" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../globalclk.sopcinfo"]
-set_global_assignment -entity "globalclk" -library "globalclk" -name SLD_INFO "QSYS_NAME globalclk HAS_SOPCINFO 1 GENERATION_ID 1586444192"
+set_global_assignment -entity "globalclk" -library "globalclk" -name SLD_INFO "QSYS_NAME globalclk HAS_SOPCINFO 1 GENERATION_ID 1588892645"
 set_global_assignment -library "globalclk" -name MISC_FILE [file join $::quartus(qip_path) "../globalclk.cmp"]
 set_global_assignment -library "globalclk" -name SLD_FILE [file join $::quartus(qip_path) "globalclk.debuginfo"]
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -15,7 +15,7 @@ set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONEN
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_REPORT_HIERARCHY "On"
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU4NjQ0NDE5Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU4ODg5MjY0NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMDhTQ00xNTNDOEc=::QXV0byBERVZJQ0U="
 set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -28,7 +28,7 @@ set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -nam
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIEZhbWlseQ=="
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfVFlQRQ==::MQ==::SG93IGRvIHlvdSB3YW50IHRvIHVzZSB0aGUgQUxUQ0xLQ1RSTD8="
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NMT0NLUw==::MQ==::SG93IG1hbnkgY2xvY2sgaW5wdXRzIHdvdWxkIHlvdSBsaWtlPw=="
-set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "R1VJX1VTRV9FTkE=::dHJ1ZQ==::Q3JlYXRlICdlbmEnIHBvcnQgdG8gZW5hYmxlIG9yIGRpc2FibGUgdGhlIGNsb2NrIG5ldHdvcmsgZHJpdmVuIGJ5IHRoaXMgYnVmZmVyPw=="
+set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "R1VJX1VTRV9FTkE=::ZmFsc2U=::Q3JlYXRlICdlbmEnIHBvcnQgdG8gZW5hYmxlIG9yIGRpc2FibGUgdGhlIGNsb2NrIG5ldHdvcmsgZHJpdmVuIGJ5IHRoaXMgYnVmZmVyPw=="
 set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "VVNFX0dMSVRDSF9GUkVFX1NXSVRDSF9PVkVSX0lNUExFTUVOVEFUSU9O::ZmFsc2U=::RW5zdXJlIGdsaXRjaC1mcmVlIHN3aXRjaG92ZXIgaW1wbGVtZW50YXRpb24="
 
 set_global_assignment -library "globalclk" -name VERILOG_FILE [file join $::quartus(qip_path) "globalclk.v"]

diff --git a/ip/clk/globalclk/synthesis/globalclk.v b/ip/clk/globalclk/synthesis/globalclk.v
@@ -5,13 +5,11 @@
 `timescale 1 ps / 1 ps
 module globalclk (
  input wire inclk, // altclkctrl_input.inclk
- input wire ena, // .ena
  output wire outclk // altclkctrl_output.outclk
  );
 
  globalclk_altclkctrl_0 altclkctrl_0 (
  .inclk (inclk), // altclkctrl_input.inclk
- .ena (ena), // .ena
  .outclk (outclk) // altclkctrl_output.outclk
  );
 

diff --git a/ip/clk/globalclk/synthesis/submodules/globalclk_altclkctrl_0.v b/ip/clk/globalclk/synthesis/submodules/globalclk_altclkctrl_0.v
@@ -88,35 +88,28 @@ endmodule //globalclk_altclkctrl_0_sub
 `timescale 1 ps / 1 ps
 // synopsys translate_on
 module globalclk_altclkctrl_0 (
- ena,
  inclk,
  outclk);
 
- input ena;
  input inclk;
  output outclk;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
- tri1 ena;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
 
  wire sub_wire0;
  wire outclk;
  wire sub_wire1;
- wire [3:0] sub_wire2;
- wire [2:0] sub_wire3;
+ wire sub_wire2;
+ wire [3:0] sub_wire3;
+ wire [2:0] sub_wire4;
 
  assign outclk = sub_wire0;
- assign sub_wire1 = inclk;
- assign sub_wire2[3:0] = {sub_wire3, sub_wire1};
- assign sub_wire3[2:0] = 3'h0;
+ assign sub_wire1 = 1'h1;
+ assign sub_wire2 = inclk;
+ assign sub_wire3[3:0] = {sub_wire4, sub_wire2};
+ assign sub_wire4[2:0] = 3'h0;
 
  globalclk_altclkctrl_0_sub globalclk_altclkctrl_0_sub_component (
- .ena (ena),
- .inclk (sub_wire2),
+ .ena (sub_wire1),
+ .inclk (sub_wire3),
  .outclk (sub_wire0));
 
 endmodule
diff --git a/rtl/sys_ctl.sv b/rtl/sys_ctl.sv
@@ -40,13 +40,11 @@ rst_sync sys_rst_n_sync(
 
 globalclk global_clk(
  .inclk(pll_200m),
- .ena(1'b1),
  .outclk(sys_clk_out)
 );
 
 globalclk global_rst_n(
  .inclk(sys_rst_n),
- .ena(1'b1),
  .outclk(sys_rst_n_out)
 );