add support for cbo.zero

coverage/rv32i_cbo.cgf

@@ -0,0 +1,14 @@
+# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
+
+cbozero:
+    config:
+      - check ISA:=regex(.*I.*Zicboz.*Zicsr.*)
+    mnemonics:
+      cbo.zero: 0
+    rs1:
+      <<: *all_regs_mx0
+    val_comb:
+      abstract_comb:
+        'walking_ones("rs1_val", 12, False)': 0
+        'walking_zeros("rs1_val", 12, False)': 0
+        'uniform_random(20, 100, ["rs1_val"], [12])': 0

coverage/rv64i_cbo.cgf

@@ -0,0 +1,14 @@
+# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
+
+cbozero:
+    config:
+      - check ISA:=regex(.*I.*Zicboz.*Zicsr.*)
+    mnemonics:
+      cbo.zero: 0
+    rs1:
+      <<: *all_regs_mx0
+    val_comb:
+      abstract_comb:
+        'walking_ones("rs1_val", 12, False)': 0
+        'walking_zeros("rs1_val", 12, False)': 0
+        'uniform_random(10, 100, ["rs1_val"], [12])': 0

riscv-ctg/CHANGELOG.md

@@ -2,11 +2,13 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-
 Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch.
 Only when a release to the main branch is done, the contents of the WIP-DEV are put under a
 versioned header while the `WIP-DEV` is left empty
 
+## [WIP-DEV]
+- Added support for zicboz extexnsion
+
 ## [0.12.2] - 2024-03-06
 - Add Zfa support. (PR#60)
 - Initial covergroups for Zvk* instructions (PR#61)
@@ -19,7 +21,7 @@ versioned header while the `WIP-DEV` is left empty
 - Add hardcoded register testcases to dataset.cgf and rv32im.cgf
 - Define rs1_val_data for c.ldsp in imc.yaml
 - Update "opcode" to "mnemonics" in the cgf files
-- Delete main.yml 
+- Delete main.yml
 - Update test.yml for CI
 - Define rs1_val_data for instructions from zicfiss.cgf in template.yaml
 - Add "warning" in the verbose definition
@@ -30,7 +32,7 @@ versioned header while the `WIP-DEV` is left empty
 - Add unratified Zaamo subcomponent of A extension
 - Add unratified B extension
 - Fix issues with csr_comb
-- Minor fix in kslraw.u in rv32ip 
+- Minor fix in kslraw.u in rv32ip
 - Fix incorrect 'sig:' entry in aes32dsi in template.yaml
 - Add sig and sz for instructions in template.yaml
 - Minor change of rd definition in c.lui in rv32ec
@@ -69,7 +71,7 @@ versioned header while the `WIP-DEV` is left empty
 
 ## [0.10.2] - 2022-10-20
 - Fixed use of lowercase LI.
-- Fixed correctval to ?? in comments. 
+- Fixed correctval to ?? in comments.
 - Fixed sw to SREG for K tests.
 - Added canaries and signature boundary labels.
 

riscv-ctg/riscv_ctg/data/template.yaml

@@ -10414,7 +10414,24 @@ czero.nez:
 
     // $comment
     // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)    
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+cbo.zero:
+  std_op:
+  sig:
+    stride: 1
+    sz: 'RVMODEL_CBZ_BLOCKSIZE'
+  xlen: [32,64]
+  isa:
+    - IZicbozZicsr
+  formattype: 'zformat'
+  rs1_op_data: *all_regs_mx0
+  rs1_val_data: 'gen_usign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op1val:$rs1_val
+    TEST_CBO_ZERO($swreg,$rs1,$inst,$rs1_val)
 
 amoadd.w:
   sig:

riscv-ctg/riscv_ctg/generator.py

@@ -112,7 +112,8 @@ def get_rm(opcode):
     'ppbrrformat': ['rs1', 'rs2', 'rd'],
     'prrformat': ['rs1', 'rs2', 'rd'],
     'prrrformat': ['rs1', 'rs2', 'rs3', 'rd'],
-    'dcasrformat': ['rs1', 'rs2', 'rd']
+    'dcasrformat': ['rs1', 'rs2', 'rd'],
+    'zformat': ['rs1']
 }
 ''' Dictionary mapping instruction formats to operands used by those formats '''
 
@@ -168,7 +169,8 @@ def get_rm(opcode):
     'ppbrrformat': '["rs1_val"] + simd_val_vars("rs2", xlen, 8)',
     'prrformat': '["rs1_val", "rs2_val"]',
     'prrrformat': "['rs1_val', 'rs2_val' , 'rs3_val']",
-    'dcasrformat': '["rs1_val", "rs2_val"]'
+    'dcasrformat': '["rs1_val", "rs2_val"]',
+    'zformat': ['rs1']
 }
 ''' Dictionary mapping instruction formats to operand value variables used by those formats '''
 
@@ -1008,6 +1010,7 @@ def valreg(self,instr_dict):
             else:
                 FLEN = 0
             XLEN = max(self.opnode['xlen'])
+            RVMODEL_CBZ_BLOCKSIZE = XLEN
             SIGALIGN = max(XLEN,FLEN)/8
             stride_sz = eval(suffix)
             template = Template(eval(self.opnode['val']['val_template']))
@@ -1320,7 +1323,7 @@ def reformat_instr(self, instr_dict):
                         value = '0x' + value[2:].zfill(int(self.xlen/4))
                         value = struct.unpack(size, bytes.fromhex(value[2:]))[0]
                     else:
-                        value = int(value)
+                        value = toint(value)
 #                    value = '0x' + struct.pack(size,value).hex()
                     #print("test",hex(value))
                     instr_dict[i][field] = hex(value)
@@ -1427,7 +1430,7 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str):
                 #         dval = (instr['rs{0}_val'.format(i)],self.iflen)
                 data.extend(instr['val_section'])
             if instr['swreg'] != sreg or eval(instr['offset'],{},
-                        {'FLEN':width,'XLEN':self.xlen,'SIGALIGN':max(self.xlen,self.flen)/8}) == 0:
+                        {'FLEN':width,'XLEN':self.xlen,'RVMODEL_CBZ_BLOCKSIZE':self.xlen, 'SIGALIGN':max(self.xlen,self.flen)/8}) == 0:
                 sign.append(signode_template.substitute(
                     {'n':n,'label':"signature_"+sreg+"_"+str(regs[sreg]),'sz':sig_sz}))
                 n = stride

riscv-test-suite/env/arch_test.h

@@ -159,7 +159,7 @@
   #define INT_CAUSE_MSK ((1<<4)-1)
 #endif
 
-        // set defaults
+// set defaults
 #ifndef   NUM_SPECD_EXCPTCAUSES
   #define NUM_SPECD_EXCPTCAUSES 16
   #define EXCPT_CAUSE_MSK ((1<<4)-1)