- Rewording

- Remove sdcsr64
- Add placeholder in appendix for exe-based imp

appendix.adoc

@@ -22,6 +22,5 @@ Similar to the Debug Module, the trace encoder is controlled by the mtrcen[i] an
 
 image::external_debug_trace.png[title="The security control on trace module",align="center"]
 
-
-
-
+=== Execution Based Implementation with Sdsec
+<TBD>

chapter2.adoc

@@ -137,7 +137,7 @@ This represents a balance between usability and hardware complexity. There may b
 [[ssdextcsr]]
 ==== Extension of Sdext CSR
 
-The `sdcsr`, `sdpc` provides supervisor read/write access to the `dcsr`, `dpc`. They are only accessible in Debug Mode. 
+The `sdcsr` and `sdpc` registers provide supervisor read/write access to the `dcsr` and `dpc` registers respectively. They are only accessible in Debug Mode. 
 
 .Allocated addresses for supervisor shadow of Debug Mode CSR  
 [options="header"]
@@ -148,10 +148,10 @@ The `sdcsr`, `sdpc` provides supervisor read/write access to the `dcsr`, `dpc`.
 | 0xaaa    | sdpc       | Supervisor debug program counter. 
 |============================================================================================
 
-The `sdcsr` is a subset of the `dcsr` formatted as shown in <<sdcsr32>> and <<sdcsr64>>, while the `sdpc` has full access to the `dpc`.
+The `sdcsr` register exposes a subset of the `dcsr`, formatted as shown in <<sdcsr32>>, while the `sdpc` provides full access to the `dpc`.
 
 [NOTE]
-Unlike `dcsr` and `dpc`, the scratch registers do not have supervisor access, and external debuggers with S-mode privilege cannot not use them as scratch memory.
+Unlike the `dcsr` and `dpc`, the scratch registers do not have supervisor access, and external debuggers with S-mode privilege cannot not use them as scratch memory.
 
 [caption="Register {counter:rimage}: ", reftext="Register {rimage}"]
 [title="Supervisor debug control and status register (sdcsr) for RV32"]
@@ -182,36 +182,6 @@ Unlike `dcsr` and `dpc`, the scratch registers do not have supervisor access, an
 ], config:{lanes: 3, hspace:1024}}
 ....
 
-[caption="Register {counter:rimage}: ", reftext="Register {rimage}"]
-[title="Supervisor debug control and status register (sdcsr) for RV64"]
-[id=sdcsr64]
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits:   1, name: 'prv'},
-  {bits:   1, name: '0'},
-  {bits:   1, name: 'step'},
-  {bits:   1, name: '0'},
-  {bits:   1, name: '0'},
-  {bits:   1, name: 'v'},
-  {bits:   3, name: 'cause'},
-  {bits:   1, name: '0'},
-  {bits:   1, name: '0'},
-  {bits:   1, name: 'stepie'},
-  {bits:   1, name: 'ebreaku'},
-  {bits:   1, name: 'ebreaks'},
-  {bits:   1, name: '0'},
-  {bits:   1, name: '0'},
-  {bits:   1, name: 'ebreakvu'},
-  {bits:   1, name: 'ebreakvs'},
-  {bits:   6, name: '0'},
-  {bits:   3, name: 'extcause'},
-  {bits:   1, name: '0'},
-  {bits:   4, name: 'debugver'},
-  {bits:   32, name: '0'},
-], config:{lanes: 4, hspace:1024}}
-....
-
 [NOTE]
 The `nmip`, `mprven`, `stoptime`, `stopcount`, `ebreakm` and `cetrig` fields in the `dcsr` are configurable only by M-mode,  masked from the `sdcsr` while the `prv` field is constrained to 1 bit.