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Clarification updates to IOMMU v1.0.1 #441

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Clarification updates to IOMMU v1.0.1 #441

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a9b21e7
editorial update
ved-rivos Oct 26, 2024
15c70fa
Clarify translation size when both stages are bare is imp-def
ved-rivos Dec 12, 2024
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8 changes: 8 additions & 0 deletions src/iommu_data_structures.adoc
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Expand Up @@ -1314,6 +1314,14 @@ This is accomplished by setting "Untranslated Access Only" (U) field of the
returned response to 1.
====

[NOTE]
====
The translation range size returned in a Success response to an ATS translation
request, when either stages of address translation are Bare, is
implementation-defined. However, it is recommended that the translation range
size be large, such as 2 MiB or 1 GiB.
====

When a Success response is generated for an ATS translation request, the setting
of the Priv, N, CXL.io, Global, and AMA fields is as follows:

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4 changes: 0 additions & 4 deletions src/iommu_in_memory_queues.adoc
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Expand Up @@ -293,10 +293,6 @@ Some implementations may cache an identity-mapped translation for the stage of
address translation operating in `Bare` mode. Since these identity mappings
are invariably correct, an explicit invalidation is unnecessary.

Some implementations may cache an identity-mapped translation for the stage of
address translation operating in `Bare` mode. Since these identity mappings
are invariably correct, an explicit invalidation is unnecessary.

A consequence of this specification is that an implementation may use any
translation for an address that was valid at any time since the most recent
`IOTINVAL` that subsumes that address. In particular, if a leaf PTE is
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13 changes: 5 additions & 8 deletions src/iommu_sw_guidelines.adoc
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Expand Up @@ -112,13 +112,10 @@ The guidelines for initializing the IOMMU are as follows:
.. If `Dw` is less than or equal to 7-bits and `1LVL` is supported then `M = 1LVL`
.. If `Dw` is less than or equal to 16-bits and `2LVL` is supported then `M = 2LVL`
.. If `Dw` is less than or equal to 24-bits and `3LVL` is supported then `M = 3LVL`

+
Program the `ddtp` register as follows:

** `temp_ddtp_var.iommu_mode = M`
** `temp_ddtp_var.PPN = B`
** `ddtp = temp_ddtp_var`
** Program the `ddtp` register as follows:
.. `temp_ddtp_var.iommu_mode = M`
.. `temp_ddtp_var.PPN = B`
.. `ddtp = temp_ddtp_var`

The IOMMU is initialized and may be now be configured with device-contexts
for devices in scope of the IOMMU.
Expand Down Expand Up @@ -384,7 +381,7 @@ following actions:
.. Process pending fault/event reports that need processing and remove them from
the `FQ` by advancing the `fqh` by the number of records processed.
. If the `ipsr.pip` bit is set then an interrupt is pending from the `PQ`.
.. Read the `pqcsr`register.
.. Read the `pqcsr` register.
.. Determine if an error caused the interrupt and if so, the cause of the error
by examining the state of the `pqmf` and `pqof` bits. If either of these bits
are set then the `PQ` encountered an error and "Page Request" reporting is
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