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Signed-off-by: Robert Chyla (MIPS) <154632854+mipsrobert@users.noreply.github.com>
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mipsrobert authored May 7, 2024
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78 changes: 39 additions & 39 deletions docs/RISC-V-Trace-Control-Interface.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -525,7 +525,7 @@ Displayed messages should report component name, component base address and curr
Many features of the Trace Encoder (TE for short) are optional. In most cases, optional features are enabled using a WARL (write any, read legal) register field. A debugger can determine if an optional feature is present by writing to the register field and reading back the result.

.*Register: trTeControl: Trace Encoder Control Register (trBaseEncoder+0x000)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|0 |trTeActive |Primary activate/reset bit for the TE. When 0, the TE may have clocks gated off or be powered
Expand Down Expand Up @@ -585,7 +585,7 @@ Trace recording/protocol format: +
|===

.*Register: trTeImpl: Trace Encoder Implementation Register (trBaseEncoder+0x004)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|3:0 |trTeVerMajor |Trace Encoder Component Major Version. Value 1 means the component is compliant with this document. Value 0 means pre-ratified/initial version - see 'Pre-ratified/Initial Interface Version' chapter at the end. |RO| 1
Expand All @@ -602,7 +602,7 @@ Trace recording/protocol format: +
NOTE: `trTeProtocol??` fields are separated from `trTeVer??` as we may have the same control interface, but protocol itself may be extended with new packets/ messages/ fields.

.*Register: trTeInstFeatures: Trace Instruction Features Register (trBaseEncoder+0x008)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|0 |trTeInstNoAddrDiff|When set, trace messages/packets always carry a full address.|WARL|0
Expand All @@ -628,7 +628,7 @@ NOTE: `trTeProtocol??` fields are separated from `trTeVer??` as we may have the
NOTE: Applicability of different `trTeInst??` fields for each trace encoding protocol is described in a document which defines the protocol (and not all fields are applicable to all protocols).

.*Register: trTeInstFilters: Trace Instruction Filters Register (trBaseEncoder+0x00C)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|15:0 |trTeInstFilters |
Expand All @@ -638,7 +638,7 @@ Determine which filters defined in <<Trace Encoder Filter Registers, Trace Encod
|===

.*Register: trTeDataControl: Data Trace Control Register (trBaseEncoder+0x010)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|0 |trTeDataImplemented|Read as 1 if data trace is implemented.|RO|SD
Expand Down Expand Up @@ -666,7 +666,7 @@ Determine which filters defined in <<Trace Encoder Filter Registers, Trace Encod
NOTE: Applicability of different `trTeData??` fields for each trace encoding protocol is described in a document which defines the protocol (and not all fields are applicable to all protocols).

.*Register: trTeDataFilters: Trace Data Filters Register (trBaseEncoder+0x01C)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|15:0 |trTeDataFilters|
Expand Down Expand Up @@ -695,7 +695,7 @@ An Internal System or Core timestamp unit may include a timestamp clock pre-scal
In a system with an Internal Core timestamp counter (implemented in Trace Encoder associated with a hart) an optional control bit is provided to stop the counter when the hart is halted by a debugger.

.*Register: trBaseEncoder/Funnel+0x040 trTsControl: Timestamp Control Register*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|0 |trTsActive |Primary activate/reset bit for timestamp unit. See <<Reset and Discovery,Reset and Discovery>> chapter for more details.|RW |0
Expand Down Expand Up @@ -730,14 +730,14 @@ Prescale timestamp clock by 2^(2*trTsPrescale) (1, 4, 16, 64).
|===

.*Register: trTsCounterLow: Timestamp Counter Lower Bits (trBaseEncoder/Funnel+0x048)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trTsCounterLow |Lower 32 bits of timestamp counter. |RO|0
|===

.*Register: trTsCounterHigh: Timestamp Counter Upper Bits (trBaseEncoder/Funnel+0x04C)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trTsCounterHigh |Upper bits of timestamp counter, zero-extended. |RO|0
Expand Down Expand Up @@ -769,7 +769,7 @@ If tracing is active (`trTeInstTracing` = 1), then the encoder generates a packe
If there are vendor-specific features that require control, the `trTeTrigDbgControl` register is used.

.*Register: trTeTrigDbgControl: Debug Trigger Control Register (trBaseEncoder+0x050)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trTeTrigDbgControl |Vendor-specific trigger setup |WARL|0
Expand All @@ -782,7 +782,7 @@ The TE may be configured with up to 8 external trigger inputs for controlling tr
External Trigger Outputs may also be present. A trigger out may be generated by trace starting, trace stopping, a watchpoint, or by other system-specific events.

.*Register: trTeTrigExtInControl: External Trigger Input Control Register (trBaseEncoder+0x054)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|3:0 |trTeTrigExtInAction0 a|
Expand All @@ -803,7 +803,7 @@ If tracing is active (`trTeInstTracing` = 1), then the encoder generates a packe
|===

.*Register: trTeTrigExtOutControl: External Trigger Output Control Register (trBaseEncoder+0x058)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|3:0 |trTeTrigExtOutEvent0 a|
Expand Down Expand Up @@ -862,7 +862,7 @@ NOTE: Filter and comparator registers refer to values of some signals (as *priv*
|===

.*Register: trTeFilter__i__Control : Filter _i_ Control Register (trBaseEncoder+0x400 + 0x20__i__)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|0 |trTeFilterEnable | Overall filter enable for filter #__i__|WARL|0
Expand Down Expand Up @@ -942,7 +942,7 @@ When `trTeFilterMatchEcause` field for filter #__i__ is set, match all excepion
|===

.*Register: trTeFilter__i__MatchValueImpdef : Filter _i_ Impdef Match Value Register (trBaseEncoder+0x410 + 0x20__i__)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trTeFilterMatchValueImpdef |
Expand All @@ -953,7 +953,7 @@ When `trTeFilterMatchimpdef` field for filter #__i__ is set, match if
|===

.*Register: trTeFilter__i__MatchMaskImpdef : Filter _i_ Impdef Match Mask Register (trBaseEncoder+0x414 + 0x20__i__)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trTeFilterMatchMaskImpdef |
Expand All @@ -964,7 +964,7 @@ When `trTeFilterMatchimpdef` field for filter #__i__ is set, match if
|===

.*Register: trTeFilter__i__MatchData : Filter _i_ Data Match Control Register (trBaseEncoder+0x418 + 0x20__i__)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|15:0 |trTeFilterMatchChoiceDtype |
Expand All @@ -979,7 +979,7 @@ for which the corresponding bit is set. For example, if bit N is 1, then match i
|===

.*Register: trTeComp__j__Control : Comparator _j_ Control Register (trBaseEncoder+0x600 + 0x20__j__)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|1:0 |trTeCompPInput |
Expand Down Expand Up @@ -1039,7 +1039,7 @@ Requires `trTeCompSInput` to be 0, and has no effect otherwise.
IMPORTANT: Comparisions are performed as unsigned numbers. Only bits from an input signal (as defined by `trTeCompPInput` and/or `trTeCompSInput` fields), should be compared. Additional most significant bits from the `trTeComp__j__PMatchLow/High` registers must be ignored.

.*Register: trTeComp__j__PMatchLow : Comparator _j_ Primary match (low) Register (trBaseEncoder+0x610 + 0x20__j__)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trTeCompPMatchLow |
Expand All @@ -1048,7 +1048,7 @@ The match value for the primary comparator (bits 31:0).
|===

.*Register: trTeComp__j__PMatchHigh : Comparator _j_ Primary match (high) Register (trBaseEncoder+0x614 + 0x20__j__)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trTeCompPMatchHigh |
Expand All @@ -1057,7 +1057,7 @@ The match value for the primary comparator (bits 63:32).
|===

.*Register: trTeComp__j__SMatchLow : Comparator _j_ Secondary match (low) Register (trBaseEncoder+0x618 + 0x20__j__)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trTeCompSMatchLow |
Expand All @@ -1066,7 +1066,7 @@ The match value for the secondary comparator (bits 31:0).
|===

.*Register: trTeComp__j__SMatchHigh : Comparator _j_ Secondary match (high) Register (trBaseEncoder+0x61C + 0x20__j__)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trTeCompSMatchHigh |
Expand All @@ -1083,7 +1083,7 @@ Trace data is placed in memory in LSB order (first byte of trace packet/data is
Be aware that in case trace memory wraps around some protocols may require additional synchronization data - it is usually done by periodically generating a sequence of alignment synchronization bytes which cannot be part of any valid packet. Specification of each trace protocol must define it.

.*Register: trRamControl: Trace RAM Sink Control Register (trBaseRam+0x000)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|0 |trRamActive |Primary activate/reset bit for Trace RAM Sink. When 0, the Trace RAM Sink may have clocks gated off or be powered
Expand Down Expand Up @@ -1112,7 +1112,7 @@ Details should be defined in definition of each trace protocol.
|===

.*Register: trRamImpl: Trace RAM Sink Implementation Register (trBaseRamSink+0x004)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|3:0 |trRamVerMajor |Trace RAM Sink Component Major Version. Value 1 means the component is compliant with this document. |RO|1
Expand All @@ -1127,7 +1127,7 @@ Details should be defined in definition of each trace protocol.
NOTE: Single RAM Sink may support both SRAM and SMEM modes, but not both of them may be enabled at the same time. It is also possible to have more than one RAM Sink in a system.

.*Register: trRamStartLow: Trace RAM Sink Start Register (trBaseRamSink+0x010)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|1:0 |--|Always 0 (two LSB of 32-bit address)|RO|0
Expand All @@ -1137,29 +1137,29 @@ NOTE: Single RAM Sink may support both SRAM and SMEM modes, but not both of them
For a bus with an address larger than 32-bit, corresponding `High` registers define the MSB part of such a larger address.

.*Register: trRamStartHigh: Trace RAM Sink Start High Bits Register (trBaseRamSink+0x014)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trRamStartHigh |High order bits (63:32) of `trRamStart` register. |WARL|Undef
|===

.*Register: trRamLimitLow: Trace RAM Sink Limit Register (trBaseRamSink+0x018)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|1:0 |--|Always 0 (two LSB of 32-bit address)|RO|0
|31:2 |trRamLimitLow |Highest absolute 32-bit part of address of trace circular buffer. The `trRamWP` register is reset to `trRamStart` after a trace word has been written to this address. |WARL|Undef
|===

.*Register: trRamLimitHigh: Trace RAM Sink Limit High Bits Register (trBaseRamSink+0x01C)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trRamLimitHigh |High order bits (63:32) of `trRamLimit` register. |WARL|Undef
|===

.*Register: trRamWPLow: Trace RAM Sink Write Pointer Register (trBaseRamSink+0x020)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|0 |trRamWrap |Set to 1 by hardware when `trRamWP` wraps. It is only set to 0 if `trRamWPLow` is written|WARL|0
Expand All @@ -1168,29 +1168,29 @@ For a bus with an address larger than 32-bit, corresponding `High` registers def
|===

.*Register: trRamWPHigh: Trace RAM Sink Write Pointer High Bits Register (trBaseRamSink+0x024)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trRamWPHigh |High order bits (63:32) of `trRamWP` register.|WARL|Undef
|===

.*Register: trRamRPLow: Trace RAM Sink Read Pointer Register (trBaseRamSink+0x028)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|1:0 |--|Always 0 (two LSB of 32-bit address)|RO|0
|31:2 |trRamRPLow |Absolute 32-bit part of address in trace circular memory buffer visible through `trRamData`. `trRamRP` auto-increments following an access to `trRamData`. After a trace word read occurs while `trRamRP` = `trRamLimit`, `trRamRP` is set to `trRamStart`. Required for SRAM mode and optional for SMEM mode. |WARL|Undef
|===

.*Register: trRamRPHigh: Trace RAM Sink Read Pointer High Bits Register (trBaseRamSink+0x02C)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trRamRPHigh |High order bits (63:32) of `trRamRP` register.|WARL|Undef
|===

.*Register: trRamData: Trace RAM Sink Data Register (trBaseRamSink+0x040)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|31:0 |trRamData |Read (and optional write) value for trace sink memory access. SRAM is always accessed by 32-bit words through this path regardless of the actual width of the sink memory. Required for SRAM mode and optional for SMEM mode. |R or RW |Undef
Expand Down Expand Up @@ -1248,7 +1248,7 @@ NOTE: Trace RAM Sink may implement writing trace by writing to `trRamData`, but
The Trace Funnel combines messages/packets from multiple sources into a single trace stream. It is implementation-dependent how many incoming messages/packets are accepted before it is switching to another input source and in what order. But a continuous stream of messages/packets at one input cannot cause other inputs to not be handled. Suggested implementation would be to process just a single message/packet from each input in a round-robin fashion.

.*Register: trFunnelControl: Trace Funnel Control Register (trBaseFunnel+0x000)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|0 |trFunnelActive |Primary activate/reset bit for trace funnel. When 0, the Trace Funnel may have clocks gated off or be powered
Expand All @@ -1260,7 +1260,7 @@ down, and other register locations may be inaccessible. Hardware may take an arb
|===

.*Register: trFunnelImpl: Trace Funnel Implementation Register (trBaseFunnel+0x004)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|3:0 |trFunnelVerMajor |Trace Funnel Component Major Version. Value 1 means the component is compliant with this document. |RO|1
Expand All @@ -1271,7 +1271,7 @@ down, and other register locations may be inaccessible. Hardware may take an arb
|===

.*Register: trFunnelDisInput: Disable Individual Funnel Inputs (trBaseFunnel+0x008)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|15:0 |trFunnelDisInput |*1:* Funnel input *#n* (bit position in register) is disabled. Incoming messages are read from diabled input but discarded.|WARL|0
Expand All @@ -1293,7 +1293,7 @@ The modes and behavior described here are intended to be compatible with trace p
*PIB Register Interface*

.*Register: trPibControl: PIB Sink Control Register (trBasePib+0x000)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|0 |trPibActive |Primary activate/reset bit for PIB Sink component. When 0, the PIB Sink may have clocks gated off or be powered
Expand Down Expand Up @@ -1321,7 +1321,7 @@ After the PIB reset value of this field should be set to safe (not too fast cloc
|===

.*Register: trPibImpl: Trace PIB Implementation Register (trBasePib+0x004)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|3:0 |trPibVerMajor |Trace PIB Sink Component Major Version. Value 1 means the component is compliant with this document. |RO|1
Expand Down Expand Up @@ -1432,7 +1432,7 @@ image:./RISC-V-Trace-Control-Interface-images/swt-uart.jpg[image]
Some SoCs may have an Advanced Trace Bus (ATB) infrastructure to manage trace produced by other components. In such systems, it may be desired to route entire RISC-V trace stream to the ATB through an ATB Bridge. This module manages the interface to ATB, generating ATB trace records that encapsulate RISC-V trace produced by the Trace Encoder[s] and/or Trace Funnel[s]. There is a control register that includes trace on/off control and a field allowing software to set the ID to be used on the ATB bus. This ID allows software to extract entire RISC-V trace from the combined trace. This interface is compatible with AMBA 4 ATB v1.1.

.*Register: trAtbBridgeControl: ATB Bridge Control Register (trAtbBridgeBase+0x000)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|0 |trAtbBridgeActive |Primary activate/reset for the ATB Bridge. When 0, the ATB Bridge may have clocks gated off or be powered
Expand All @@ -1446,7 +1446,7 @@ down, and other register locations may be inaccessible. Hardware may take an arb
|===

.*Register: trAtbBridgeImpl: ATB Bridge Implementation Register (trAtbBridgeBase+0x004)*
[cols="5%,30%,~,8%,8%",options="header",]
[cols="6%,30%,~,8%,8%",options="header",]
|===
|*Bit* |*Field* |*Description* |*RW* |*Reset*
|3:0 |trAtbBridgeVerMajor |ATB Bridge Component Major Version. Value 1 means the component is compliant with this document. |RO|1
Expand Down

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