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Add support for the Zfa ISA extension #60
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cmuellner
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Apr 6, 2023
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point extensions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)
Zfa defines its instructions in combination with the following
extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
Since the RISC-V architecture test framework does not support
the RISC-V quad-precision floating-point ISA extension (Q) and
the RISC-V half-precision floating-point ISA extension (Zfh),
this patch does not include tests for instructions that depend
on these extensions.
Given missing infrastructure support, the fli.* instruction tests
are hand written and not generated.
All other test files are generated using riscv-ctg.
The generated test files have been generated using the following
command (with $BASEISA={rv32i,rv64i} and $FLEN={32,64}):
riscv_ctg.py \
--cgf coverage/dataset.cgf \
--cgf coverage/zicond.cgf \
--base-isa $BASEISA \
--flen $FLEN \
-d tests_$BASEISA_$FLEN/
Exceptions are:
* fcvtmod.w.d.cgf is for FLEN=32 only
* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only
The resulting tests have been copied to the target directory.
The generation of the Zfa test cases depends on a PR in the riscv-ctg
repository:
riscv-software-src/riscv-ctg#60
The Zfa specification is not frozen at the moment (which is why this
patch is RFC) and can be found here:
https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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cmuellner
added a commit
to cmuellner/riscv-arch-test
that referenced
this pull request
May 10, 2023
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point extensions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)
Zfa defines its instructions in combination with the following
extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
Since the RISC-V architecture test framework does not support
the RISC-V quad-precision floating-point ISA extension (Q) and
the RISC-V half-precision floating-point ISA extension (Zfh),
this patch does not include tests for instructions that depend
on these extensions.
Given missing infrastructure support, the fli.* instruction tests
are hand written and not generated.
All other test files are generated using riscv-ctg.
The generated test files have been generated using the following
command (with $BASEISA={rv32i,rv64i} and $FLEN={32,64}):
riscv_ctg.py \
--cgf coverage/dataset.cgf \
--cgf coverage/zicond.cgf \
--base-isa $BASEISA \
--flen $FLEN \
-d tests_$BASEISA_$FLEN/
Exceptions are:
* fcvtmod.w.d.cgf is for FLEN=32 only
* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only
The resulting tests have been copied to the target directory.
The generation of the Zfa test cases depends on a PR in the riscv-ctg
repository:
riscv-software-src/riscv-ctg#60
The Zfa specification is not frozen at the moment (which is why this
patch is RFC) and can be found here:
https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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Updated PR:
|
cmuellner
added a commit
to cmuellner/riscv-arch-test
that referenced
this pull request
May 23, 2023
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point extensions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)
Zfa defines its instructions in combination with the following
extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
Since the RISC-V architecture test framework does not support
the RISC-V quad-precision floating-point ISA extension (Q) and
the RISC-V half-precision floating-point ISA extension (Zfh),
this patch does not include tests for instructions that depend
on these extensions.
Given missing infrastructure support, the fli.* instruction tests
are hand written and not generated.
All other test files are generated using riscv-ctg.
The generated test files have been generated using the following
command (with $BASEISA={rv32i,rv64i} and $FLEN={32,64}):
riscv_ctg.py \
--cgf coverage/dataset.cgf \
--cgf coverage/zicond.cgf \
--base-isa $BASEISA \
--flen $FLEN \
-d tests_$BASEISA_$FLEN/
Exceptions are:
* fcvtmod.w.d.cgf is for FLEN=32 only
* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only
The resulting tests have been copied to the target directory.
The generation of the Zfa test cases depends on a PR in the riscv-ctg
repository:
riscv-software-src/riscv-ctg#60
The Zfa specification is not frozen at the moment (which is why this
patch is RFC) and can be found here:
https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
cmuellner
added a commit
to cmuellner/riscv-arch-test
that referenced
this pull request
May 23, 2023
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point extensions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)
Zfa defines its instructions in combination with the following
extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
Since the RISC-V architecture test framework does not support
the RISC-V quad-precision floating-point ISA extension (Q) and
the RISC-V half-precision floating-point ISA extension (Zfh),
this patch does not include tests for instructions that depend
on these extensions.
Given missing infrastructure support, the fli.* instruction tests
are hand written and not generated.
All other test files are generated using riscv-ctg.
The generated test files have been generated using the following
command (with $BASEISA={rv32i,rv64i} and $FLEN={32,64}):
riscv_ctg.py \
--cgf coverage/dataset.cgf \
--cgf coverage/zicond.cgf \
--base-isa $BASEISA \
--flen $FLEN \
-d tests_$BASEISA_$FLEN/
Exceptions are:
* fcvtmod.w.d.cgf is for FLEN=32 only
* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only
The resulting tests have been copied to the target directory.
The generation of the Zfa test cases depends on a PR in the riscv-ctg
repository:
riscv-software-src/riscv-ctg#60
The Zfa specification is not frozen at the moment (which is why this
patch is RFC) and can be found here:
https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
|
@cmuellner could you try rebase this PR again, we think the issue riscv-non-isa/riscv-arch-test#331 got fixed already. please use latest riscv-arch-test repo |
|
I've rebased the PR. |
cmuellner
added a commit
to cmuellner/riscv-arch-test
that referenced
this pull request
Jan 16, 2024
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point extensions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)
Zfa defines its instructions in combination with the following
extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
Since the RISC-V architecture test framework does not support
the RISC-V quad-precision floating-point ISA extension (Q) and
the RISC-V half-precision floating-point ISA extension (Zfh),
this patch does not include tests for instructions that depend
on these extensions.
Given missing infrastructure support, the fli.* instruction tests
are hand written and not generated.
All other test files are generated using riscv-ctg.
The generated test files have been generated using the following
command (with $BASEISA={rv32i,rv64i} and $FLEN={32,64}):
riscv_ctg.py \
--cgf coverage/dataset.cgf \
--cgf coverage/zicond.cgf \
--base-isa $BASEISA \
--flen $FLEN \
-d tests_$BASEISA_$FLEN/
Exceptions are:
* fcvtmod.w.d.cgf is for FLEN=32 only
* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only
The resulting tests have been copied to the target directory.
The generation of the Zfa test cases depends on a PR in the riscv-ctg
repository:
riscv-software-src/riscv-ctg#60
The Zfa specification is not frozen at the moment (which is why this
patch is RFC) and can be found here:
https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
|
I've rebased the PR and addressed an issue with the generation of tests for the froundnx instruction. |
The recently introduced toint() function does not accept arguments of type int and will trigger an exception in this case. This leads to an always crashing code path in generator.py, where rm_dict[] maps the rounding mode string to an integer, that is then passed to toint(). There are several ways to address this (e.g. mapping to a string, or making toint() more robust), but dropping the call to toint() is obviously the right thing to do. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch introduces the RISC-V Zfa extension, which introduces additional floating-point extensions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of float register bigger than XLEN * Quiet comparison instructions (fleq/fltq) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) Since riscv-ctg does not support the RISC-V quad-precision floating-point ISA extension (Q) as well as the RISC-V half-precision floating-point ISA extension (Zfh), this patch does not include the instructions that depend on these extensions. All other instructions are included in this patch. The instruction descriptions (simple_cgfs/zfa/*) use different instructions as parameter for the coverpoint generator functions (e.g. fleq.s uses "fle.s") to circumvent documented limitations of these generator functions. Technically there is no reason to adjust generator.py. All required information could be extracted from instruction descriptions. However, that is not the case, and the file also includes its own hard-coded assumptions, which have to be adjusted as well. The Zfa specification can be found here: https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
There is not much infrastucture support for the fli* instructions. Let's add a cgf that defines the instruction's covergroup with the existing infrastructure support. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
The specification of fcvtmod requires a rounding mode of 'rtz'. Let's restrict the generated test cases accordingly. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This fixes a typo in the mnemonics name which prevents the creation of froundnx test cases. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
A typo in the instruction definition prevented the creation of fmvp.d.x test cases. Let's fix that. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
The specification of fcvtmod requires a rounding mode of 'rtz'. Recently we have added a commit to restrict the rounding modes accoringly. However, that turned out to be unsufficient. Therefore, this patch directly sets the rounding mode to 'rtz'. As a result this patch only generates 'rtz' test cases. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
|
Updated PR: Added a commit to make the |
cmuellner
added a commit
to cmuellner/riscv-arch-test
that referenced
this pull request
Apr 2, 2024
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point extensions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)
Zfa defines its instructions in combination with the following
extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
Since the RISC-V architecture test framework does not support
the RISC-V quad-precision floating-point ISA extension (Q) and
the RISC-V half-precision floating-point ISA extension (Zfh),
this patch does not include tests for instructions that depend
on these extensions.
Given missing infrastructure support, the fli.* instruction tests
are hand written and not generated.
All other test files are generated using riscv-ctg.
The generated test files have been generated using the following
command (with $BASEISA={rv32i,rv64i}, $FLEN={32,64}), and CFG=$INSN:
riscv_ctg.py \
--cgf sample_cgfs/dataset.cgf \
--cgf sample_cgfs/zfa/$CGF \
--base-isa $BASEISA \
--flen $FLEN \
-d tests_$BASEISA_$FLEN/
Exceptions are:
* fcvtmod.w.d.cgf is for FLEN=32 only
* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only
The resulting tests have been copied to the target directory.
The generation of the Zfa test cases depends on a PR in the riscv-ctg
repository:
riscv-software-src/riscv-ctg#60
The Zfa specification is ratified and can be found here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zfa.adoc
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Bump the CTG version to 0.12.2. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
|
Updated |
|
@UmerShahidengr could you review this PR |
UmerShahidengr
approved these changes
May 3, 2024
Closed
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This patch introduces the RISC-V Zfa extension, which introduces additional floating-point extensions:
Zfa defines its instructions in combination with the following extensions:
Since riscv-ctg does not support the RISC-V quad-precision floating-point ISA extension (Q) as well as the RISC-V half-precision floating-point ISA extension (Zfh), this patch does not include the instructions that depend on these extensions. All other instructions are included in this patch.
The instruction descriptions (simple_cgfs/zfa/*) use different instructions as parameter for the coverpoint generator functions (e.g. fleq.s uses "fle.s") to circumvent documented limitations of these generator functions.
Technically there is no reason to adjust generator.py. All required information could be extracted from instruction descriptions. However, that is not the case, and the file also includes its own hard-coded assumptions, which have to be adjusted as well.
The Zfa specification can be found here:
https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex