Initial covergroups for Zvk* instructions

CHANGELOG.md

@@ -2,12 +2,14 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+
 Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch.
 Only when a release to the main branch is done, the contents of the WIP-DEV are put under a
 versioned header while the `WIP-DEV` is left empty
 
 ## [0.12.2] - 2024-03-06
-- Add Zfa support.
+- Add Zfa support. (PR#60)
+- Initial covergroups for Zvk* instructions (PR#61)
 
 ## [0.12.1] - 2024-02-27
 - Fix test.yml

sample_cgfs/dataset.cgf

@@ -120,6 +120,40 @@ datasets:
     f30: 0
     f31: 0
 
+  all_vregs: &all_vregs
+    v0: 0
+    v1: 0
+    v2: 0
+    v3: 0
+    v4: 0
+    v5: 0
+    v6: 0
+    v7: 0
+    v8: 0
+    v9: 0
+    v10: 0
+    v11: 0
+    v12: 0
+    v13: 0
+    v14: 0
+    v15: 0
+    v16: 0
+    v17: 0
+    v18: 0
+    v19: 0
+    v20: 0
+    v21: 0
+    v22: 0
+    v23: 0
+    v24: 0
+    v25: 0
+    v26: 0
+    v27: 0
+    v28: 0
+    v29: 0
+    v30: 0
+    v31: 0
+
   pair_regs: &pair_regs
     x2: 0
     x4: 0

sample_cgfs/zvk/vaesdf.cgf

@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaesdf.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesdf.vv: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0
+
+vaesdf.vs:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesdf.vs: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaesdm.cgf

@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaesdm.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesdm.vv: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0
+
+vaesdm.vs:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesdm.vs: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaesef.cgf

@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaesef.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesef.vv: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0
+
+vaesef.vs:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesef.vs: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaesem.cgf

@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaesem.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesem.vv: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0
+
+vaesem.vs:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesem.vs: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaeskf1.cgf

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaeskf1.vi:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaeskf1.vi: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaeskf2.cgf

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaeskf2.vi:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaeskf2.vi: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaesz.cgf

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaesz.vs:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesz.vs: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0
+
+

sample_cgfs/zvk/vandn.cgf

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vandn.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vandn.vv: 0
+    rs1:
+      <<: *all_vregs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb
+
+vandn.vx:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vandn.vx: 0
+    rs1:
+      <<: *all_regs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb

sample_cgfs/zvk/vbrev8.cgf

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vbrev8.v:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vbrev8.v: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vclmul.cgf

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vclmul.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vclmul.vv: 0
+    rs1:
+      <<: *all_vregs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb
+
+vclmul.vx:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vclmul.vx: 0
+    rs1:
+      <<: *all_regs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb

sample_cgfs/zvk/vclmulh.cgf

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vclmulh.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vclmulh.vv: 0
+    rs1:
+      <<: *all_vregs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb
+
+vclmulh.vx:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vclmulh.vx: 0
+    rs1:
+      <<: *all_regs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb

sample_cgfs/zvk/vghsh.cgf

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vghsh.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkg)
+    mnemonics:
+      vghsh.vv: 0
+    rs1:
+      <<: *all_vregs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb

sample_cgfs/zvk/vgmul.cgf

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vgmul.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkg)
+    mnemonics:
+      vgmul.vv: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vrev8.cgf

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vrev8.v:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vrev8.v: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vrol.cgf

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vrol.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vrol.vv: 0
+    rs1:
+      <<: *all_vregs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb
+
+vrol.vx:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vrol.vx: 0
+    rs1:
+      <<: *all_regs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb