Merge branch 'master' into CDE

Signed-off-by: Andrew Waterman <andrew@sifive.com>

constants.py

@@ -2,6 +2,20 @@
 import csv
 
 
+overlapping_extensions = {
+    'rv_zcmt': {'rv_c_d'},
+    'rv_zcmp': {'rv_c_d'},
+    'rv_c': {'rv_zcmop'},
+}
+
+overlapping_instructions = {
+    'c_addi': {'c_nop'},
+    'c_lui': {'c_addi16sp'},
+    'c_mv': {'c_jr'},
+    'c_jalr': {'c_ebreak'},
+    'c_add': {'c_ebreak', 'c_jalr'},
+}
+
 isa_regex = \
 re.compile("^RV(32|64|128)[IE]+[ABCDEFGHJKLMNPQSTUVX]*(Zicsr|Zifencei|Zihintpause|Zam|Ztso|Zkne|Zknd|Zknh|Zkse|Zksh|Zkg|Zkb|Zkr|Zks|Zkn|Zba|Zbc|Zbb|Zbp|Zbr|Zbm|Zbs|Zbe|Zbf|Zbt|Zmmul|Zbpbo|Zca|Zcf|Zcd|Zcb|Zcmp|Zcmt){,1}(_Zicsr){,1}(_Zifencei){,1}(_Zihintpause){,1}(_Zmmul){,1}(_Zam){,1}(_Zba){,1}(_Zbb){,1}(_Zbc){,1}(_Zbe){,1}(_Zbf){,1}(_Zbm){,1}(_Zbp){,1}(_Zbpbo){,1}(_Zbr){,1}(_Zbs){,1}(_Zbt){,1}(_Zkb){,1}(_Zkg){,1}(_Zkr){,1}(_Zks){,1}(_Zkn){,1}(_Zknd){,1}(_Zkne){,1}(_Zknh){,1}(_Zkse){,1}(_Zksh){,1}(_Ztso){,1}(_Zca){,1}(_Zcf){,1}(_Zcd){,1}(_Zcb){,1}(_Zcmp){,1}(_Zcmt){,1}$")
 
@@ -157,11 +171,8 @@
     'rstsa16',
     'rstsa32',
     'srli32_u',
-    'slli_rv128',
     'slli_rv32',
-    'srai_rv128',
     'srai_rv32',
-    'srli_rv128',
     'srli_rv32',
     'umax32',
     'c_mop_1',

encoding.h

@@ -21,6 +21,7 @@
 #define MSTATUS_TW          0x00200000
 #define MSTATUS_TSR         0x00400000
 #define MSTATUS_SPELP       0x00800000
+#define MSTATUS_SDT         0x01000000
 #define MSTATUS32_SD        0x80000000
 #define MSTATUS_UXL         0x0000000300000000
 #define MSTATUS_SXL         0x0000000C00000000
@@ -29,12 +30,14 @@
 #define MSTATUS_GVA         0x0000004000000000
 #define MSTATUS_MPV         0x0000008000000000
 #define MSTATUS_MPELP       0x0000020000000000
+#define MSTATUS_MDT         0x0000040000000000
 #define MSTATUS64_SD        0x8000000000000000
 
 #define MSTATUSH_SBE        0x00000010
 #define MSTATUSH_MBE        0x00000020
 #define MSTATUSH_GVA        0x00000040
 #define MSTATUSH_MPV        0x00000080
+#define MSTATUSH_MDT        0x00000400
 
 #define SSTATUS_UIE         0x00000001
 #define SSTATUS_SIE         0x00000002
@@ -48,6 +51,7 @@
 #define SSTATUS_SUM         0x00040000
 #define SSTATUS_MXR         0x00080000
 #define SSTATUS_SPELP       0x00800000
+#define SSTATUS_SDT         0x01000000
 #define SSTATUS32_SD        0x80000000
 #define SSTATUS_UXL         0x0000000300000000
 #define SSTATUS64_SD        0x8000000000000000
@@ -70,19 +74,22 @@
 #define MNSTATUS_MNPP       0x00001800
 #define MNSTATUS_MNPV       0x00000080
 
-#define DCSR_XDEBUGVER      (3U<<30)
-#define DCSR_NDRESET        (1<<29)
-#define DCSR_FULLRESET      (1<<28)
+#define DCSR_XDEBUGVER      (15U<<28)
+#define DCSR_EXTCAUSE       (7<<24)
+#define DCSR_CETRIG         (1<<19)
 #define DCSR_PELP           (1<<18)
+#define DCSR_EBREAKVS       (1<<17)
+#define DCSR_EBREAKVU       (1<<16)
 #define DCSR_EBREAKM        (1<<15)
-#define DCSR_EBREAKH        (1<<14)
 #define DCSR_EBREAKS        (1<<13)
 #define DCSR_EBREAKU        (1<<12)
-#define DCSR_STOPCYCLE      (1<<10)
+#define DCSR_STEPIE         (1<<11)
+#define DCSR_STOPCOUNT      (1<<10)
 #define DCSR_STOPTIME       (1<<9)
 #define DCSR_CAUSE          (7<<6)
-#define DCSR_DEBUGINT       (1<<5)
-#define DCSR_HALT           (1<<3)
+#define DCSR_V              (1<<5)
+#define DCSR_MPRVEN         (1<<4)
+#define DCSR_NMIP           (1<<3)
 #define DCSR_STEP           (1<<2)
 #define DCSR_PRV            (3<<0)
 
@@ -141,6 +148,8 @@
 #define MIP_MEIP            (1 << IRQ_M_EXT)
 #define MIP_SGEIP           (1 << IRQ_S_GEXT)
 #define MIP_LCOFIP          (1 << IRQ_LCOF)
+#define MIP_RAS_LOW_PRIO    (1ULL << IRQ_RAS_LOW_PRIO)
+#define MIP_RAS_HIGH_PRIO   (1ULL << IRQ_RAS_HIGH_PRIO)
 
 #define MIP_S_MASK          (MIP_SSIP | MIP_STIP | MIP_SEIP)
 #define MIP_VS_MASK         (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
@@ -158,11 +167,13 @@
 #define MENVCFG_CBCFE 0x00000040
 #define MENVCFG_CBZE  0x00000080
 #define MENVCFG_CDE   0x1000000000000000
+#define MENVCFG_DTE   0x0800000000000000
 #define MENVCFG_ADUE  0x2000000000000000
 #define MENVCFG_PBMTE 0x4000000000000000
 #define MENVCFG_STCE  0x8000000000000000
 
 #define MENVCFGH_CDE   0x10000000
+#define MENVCFGH_DTE   0x08000000
 #define MENVCFGH_ADUE  0x20000000
 #define MENVCFGH_PBMTE 0x40000000
 #define MENVCFGH_STCE  0x80000000
@@ -172,11 +183,15 @@
 #define MSTATEEN0_JVT      0x00000004
 #define MSTATEEN0_PRIV114  0x0080000000000000
 #define MSTATEEN0_HCONTEXT 0x0200000000000000
+#define MSTATEEN0_AIA      0x0800000000000000
+#define MSTATEEN0_CSRIND   0x1000000000000000
 #define MSTATEEN0_HENVCFG  0x4000000000000000
 #define MSTATEEN_HSTATEEN  0x8000000000000000
 
 #define MSTATEEN0H_PRIV114  0x00800000
 #define MSTATEEN0H_HCONTEXT 0x02000000
+#define MSTATEEN0H_AIA      0x08000000
+#define MSTATEEN0H_CSRIND   0x10000000
 #define MSTATEEN0H_HENVCFG  0x40000000
 #define MSTATEENH_HSTATEEN  0x80000000
 
@@ -200,10 +215,12 @@
 #define HENVCFG_CBIE  0x00000030
 #define HENVCFG_CBCFE 0x00000040
 #define HENVCFG_CBZE  0x00000080
+#define HENVCFG_DTE   0x0800000000000000
 #define HENVCFG_ADUE  0x2000000000000000
 #define HENVCFG_PBMTE 0x4000000000000000
 #define HENVCFG_STCE  0x8000000000000000
 
+#define HENVCFGH_DTE   0x08000000
 #define HENVCFGH_ADUE  0x20000000
 #define HENVCFGH_PBMTE 0x40000000
 #define HENVCFGH_STCE  0x80000000
@@ -224,10 +241,14 @@
 #define HSTATEEN0_FCSR     0x00000002
 #define HSTATEEN0_JVT      0x00000004
 #define HSTATEEN0_SCONTEXT 0x0200000000000000
+#define HSTATEEN0_AIA      0x0800000000000000
+#define HSTATEEN0_CSRIND   0x1000000000000000
 #define HSTATEEN0_SENVCFG  0x4000000000000000
 #define HSTATEEN_SSTATEEN  0x8000000000000000
 
 #define HSTATEEN0H_SCONTEXT 0x02000000
+#define HSTATEEN0H_AIA      0x08000000
+#define HSTATEEN0H_CSRIND   0x10000000
 #define HSTATEEN0H_SENVCFG  0x40000000
 #define HSTATEENH_SSTATEEN  0x80000000
 
@@ -307,21 +328,23 @@
 #define PMP_NA4   0x10
 #define PMP_NAPOT 0x18
 
-#define IRQ_U_SOFT   0
-#define IRQ_S_SOFT   1
-#define IRQ_VS_SOFT  2
-#define IRQ_M_SOFT   3
-#define IRQ_U_TIMER  4
-#define IRQ_S_TIMER  5
-#define IRQ_VS_TIMER 6
-#define IRQ_M_TIMER  7
-#define IRQ_U_EXT    8
-#define IRQ_S_EXT    9
-#define IRQ_VS_EXT   10
-#define IRQ_M_EXT    11
-#define IRQ_S_GEXT   12
-#define IRQ_COP      12
-#define IRQ_LCOF     13
+#define IRQ_U_SOFT        0
+#define IRQ_S_SOFT        1
+#define IRQ_VS_SOFT       2
+#define IRQ_M_SOFT        3
+#define IRQ_U_TIMER       4
+#define IRQ_S_TIMER       5
+#define IRQ_VS_TIMER      6
+#define IRQ_M_TIMER       7
+#define IRQ_U_EXT         8
+#define IRQ_S_EXT         9
+#define IRQ_VS_EXT        10
+#define IRQ_M_EXT         11
+#define IRQ_S_GEXT        12
+#define IRQ_COP           12
+#define IRQ_LCOF          13
+#define IRQ_RAS_LOW_PRIO  35
+#define IRQ_RAS_HIGH_PRIO 43
 
 /* page table entry (PTE) fields */
 #define PTE_V     0x001 /* Valid */
@@ -348,6 +371,7 @@
 
 /* software check exception xtval codes */
 #define LANDING_PAD_FAULT 2
+#define SHADOW_STACK_FAULT 3
 
 #ifdef __riscv
 

parse.py

@@ -133,7 +133,7 @@ def process_enc_line(line, ext):
 
     return (name, single_dict)
 
-def same_base_ext (ext_name, ext_name_list):
+def same_base_isa(ext_name, ext_name_list):
     type1 = ext_name.split("_")[0]
     for ext_name1 in ext_name_list:
         type2 = ext_name1.split("_")[0]
@@ -144,6 +144,26 @@ def same_base_ext (ext_name, ext_name_list):
             return True
     return False
 
+def overlaps(x, y):
+    x = x.rjust(len(y), '-')
+    y = y.rjust(len(x), '-')
+
+    for i in range(0, len(x)):
+        if not (x[i] == '-' or y[i] == '-' or x[i] == y[i]):
+            return False
+
+    return True
+
+def overlap_allowed(a, x, y):
+    return x in a and y in a[x] or \
+           y in a and x in a[y]
+
+def extension_overlap_allowed(x, y):
+    return overlap_allowed(overlapping_extensions, x, y)
+
+def instruction_overlap_allowed(x, y):
+    return overlap_allowed(overlapping_instructions, x, y)
+
 def create_inst_dict(file_filter, include_pseudo=False, include_pseudo_ops=[]):
     '''
     This function return a dictionary containing all instructions associated
@@ -222,29 +242,32 @@ def create_inst_dict(file_filter, include_pseudo=False, include_pseudo_ops=[]):
             # instruction is already imported and raise SystemExit
             if name in instr_dict:
                 var = instr_dict[name]["extension"]
-                if same_base_ext(ext_name, var):
-                    # disable same names on the same base extensions
+                if same_base_isa(ext_name, var):
+                    # disable same names on the same base ISA
                     err_msg = f'instruction : {name} from '
                     err_msg += f'{ext_name} is already '
-                    err_msg += f'added from {var} in same base extensions'
+                    err_msg += f'added from {var} in same base ISA'
                     logging.error(err_msg)
                     raise SystemExit(1)
                 elif instr_dict[name]['encoding'] != single_dict['encoding']:
-                    # disable same names with different encodings on different base extensions
+                    # disable same names with different encodings on different base ISAs
                     err_msg = f'instruction : {name} from '
                     err_msg += f'{ext_name} is already '
-                    err_msg += f'added from {var} but each have different encodings in different base extensions'
+                    err_msg += f'added from {var} but each have different encodings in different base ISAs'
                     logging.error(err_msg)
                     raise SystemExit(1)
                 instr_dict[name]['extension'].extend(single_dict['extension'])
             else:
               for key in instr_dict:
                   item = instr_dict[key]
-                  if item["encoding"] == single_dict['encoding'] and same_base_ext(ext_name, item["extension"]):
-                      # disable different names with same encodings on the same base extensions
-                      err_msg = f'instruction : {name} from '
-                      err_msg += f'{ext_name} has the same encoding with instruction {key} '
-                      err_msg += f'added from {item["extension"]} in same base extensions'
+                  if overlaps(item['encoding'], single_dict['encoding']) and \
+                    not extension_overlap_allowed(ext_name, item['extension'][0]) and \
+                    not instruction_overlap_allowed(name, key) and \
+                    same_base_isa(ext_name, item['extension']):
+                      # disable different names with overlapping encodings on the same base ISA
+                      err_msg = f'instruction : {name} in extension '
+                      err_msg += f'{ext_name} overlaps instruction {key} '
+                      err_msg += f'in extension {item["extension"]}'
                       logging.error(err_msg)
                       raise SystemExit(1)
 
@@ -756,9 +779,7 @@ def make_chisel(instr_dict, spinal_hdl=False):
         extensions = instr_dict_2_extensions(instr_dict)
         for e in extensions:
             e_instrs = filter(lambda i: instr_dict[i]['extension'][0] == e, instr_dict)
-            if "rv128_" in e:
-                e_format = e.replace("rv128_", "").upper() + "128"
-            elif "rv64_" in e:
+            if "rv64_" in e:
                 e_format = e.replace("rv64_", "").upper() + "64"
             elif "rv32_" in e:
                 e_format = e.replace("rv32_", "").upper() + "32"

rv32_zbb

@@ -1,3 +1,3 @@
-$pseudo_op rv_zbe::pack     zext.h.rv32 rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33
+$pseudo_op rv_zbkb::pack     zext.h.rv32 rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33
 $pseudo_op rv64_zbp::grevi  rev8.rv32 rd rs1   31..20=0x698 14..12=5 6..0=0x13
 $pseudo_op rv64_zbb::rori   rori.rv32 rd rs1   31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3

rv64_zbb

@@ -5,5 +5,5 @@ rolw  rd rs1 rs2                            31..25=0x30 14..12=1 6..2=0x0E 1..0=
 rorw  rd rs1 rs2                            31..25=0x30 14..12=5 6..2=0x0E 1..0=3
 roriw rd rs1                                31..25=0x30 shamtw 14..12=5 6..2=0x06 1..0=3
 rori  rd rs1                                31..26=0x18 shamtd 14..12=5 6..2=0x04 1..0=3
-$pseudo_op rv64_zbe::packw zext.h rd rs1    31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3 
+$pseudo_op rv64_zbkb::packw zext.h rd rs1    31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3 
 $pseudo_op rv64_zbp::grevi rev8 rd rs1      31..20=0x6B8 14..12=5 6..0=0x13

rv64_zbkb

@@ -3,4 +3,4 @@ $import rv64_zbb::rolw
 $import rv64_zbb::rorw
 $import rv64_zbb::roriw
 $import rv64_zbb::rori
-$import rv64_zbe::packw
+packw      rd rs1 rs2 31..25=4  14..12=4 6..2=0x0E 1..0=3

rv64_zk

@@ -4,7 +4,7 @@ $import rv64_zbb::rolw
 $import rv64_zbb::rorw
 $import rv64_zbb::roriw
 $import rv64_zbb::rori
-$import rv64_zbe::packw
+$import rv64_zbkb::packw
 
 #import zkne
 # Scalar AES - RV64

rv64_zkn

@@ -4,7 +4,7 @@ $import rv64_zbb::rolw
 $import rv64_zbb::rorw
 $import rv64_zbb::roriw
 $import rv64_zbb::rori
-$import rv64_zbe::packw
+$import rv64_zbkb::packw
 
 #import zkne
 # Scalar AES - RV64

rv64_zks

@@ -4,4 +4,4 @@ $import rv64_zbb::rolw
 $import rv64_zbb::rorw
 $import rv64_zbb::roriw
 $import rv64_zbb::rori
-$import rv64_zbe::packw
+$import rv64_zbkb::packw