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tariqkurd-repo committed May 16, 2024
2 parents 239ce02 + a50bc1f commit 28e726e
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17 changes: 14 additions & 3 deletions constants.py
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,20 @@
import csv


overlapping_extensions = {
'rv_zcmt': {'rv_c_d'},
'rv_zcmp': {'rv_c_d'},
'rv_c': {'rv_zcmop'},
}

overlapping_instructions = {
'c_addi': {'c_nop'},
'c_lui': {'c_addi16sp'},
'c_mv': {'c_jr'},
'c_jalr': {'c_ebreak'},
'c_add': {'c_ebreak', 'c_jalr'},
}

isa_regex = \
re.compile("^RV(32|64|128)[IE]+[ABCDEFGHJKLMNPQSTUVX]*(Zicsr|Zifencei|Zihintpause|Zam|Ztso|Zkne|Zknd|Zknh|Zkse|Zksh|Zkg|Zkb|Zkr|Zks|Zkn|Zba|Zbc|Zbb|Zbp|Zbr|Zbm|Zbs|Zbe|Zbf|Zbt|Zmmul|Zbpbo|Zca|Zcf|Zcd|Zcb|Zcmp|Zcmt){,1}(_Zicsr){,1}(_Zifencei){,1}(_Zihintpause){,1}(_Zmmul){,1}(_Zam){,1}(_Zba){,1}(_Zbb){,1}(_Zbc){,1}(_Zbe){,1}(_Zbf){,1}(_Zbm){,1}(_Zbp){,1}(_Zbpbo){,1}(_Zbr){,1}(_Zbs){,1}(_Zbt){,1}(_Zkb){,1}(_Zkg){,1}(_Zkr){,1}(_Zks){,1}(_Zkn){,1}(_Zknd){,1}(_Zkne){,1}(_Zknh){,1}(_Zkse){,1}(_Zksh){,1}(_Ztso){,1}(_Zca){,1}(_Zcf){,1}(_Zcd){,1}(_Zcb){,1}(_Zcmp){,1}(_Zcmt){,1}$")

Expand Down Expand Up @@ -157,11 +171,8 @@
'rstsa16',
'rstsa32',
'srli32_u',
'slli_rv128',
'slli_rv32',
'srai_rv128',
'srai_rv32',
'srli_rv128',
'srli_rv32',
'umax32',
'c_mop_1',
Expand Down
34 changes: 27 additions & 7 deletions encoding.h
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@
#define MSTATUS_TW 0x00200000
#define MSTATUS_TSR 0x00400000
#define MSTATUS_SPELP 0x00800000
#define MSTATUS_SDT 0x01000000
#define MSTATUS32_SD 0x80000000
#define MSTATUS_UXL 0x0000000300000000
#define MSTATUS_SXL 0x0000000C00000000
Expand All @@ -29,12 +30,14 @@
#define MSTATUS_GVA 0x0000004000000000
#define MSTATUS_MPV 0x0000008000000000
#define MSTATUS_MPELP 0x0000020000000000
#define MSTATUS_MDT 0x0000040000000000
#define MSTATUS64_SD 0x8000000000000000

#define MSTATUSH_SBE 0x00000010
#define MSTATUSH_MBE 0x00000020
#define MSTATUSH_GVA 0x00000040
#define MSTATUSH_MPV 0x00000080
#define MSTATUSH_MDT 0x00000400

#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
Expand All @@ -48,6 +51,7 @@
#define SSTATUS_SUM 0x00040000
#define SSTATUS_MXR 0x00080000
#define SSTATUS_SPELP 0x00800000
#define SSTATUS_SDT 0x01000000
#define SSTATUS32_SD 0x80000000
#define SSTATUS_UXL 0x0000000300000000
#define SSTATUS64_SD 0x8000000000000000
Expand All @@ -70,19 +74,22 @@
#define MNSTATUS_MNPP 0x00001800
#define MNSTATUS_MNPV 0x00000080

#define DCSR_XDEBUGVER (3U<<30)
#define DCSR_NDRESET (1<<29)
#define DCSR_FULLRESET (1<<28)
#define DCSR_XDEBUGVER (15U<<28)
#define DCSR_EXTCAUSE (7<<24)
#define DCSR_CETRIG (1<<19)
#define DCSR_PELP (1<<18)
#define DCSR_EBREAKVS (1<<17)
#define DCSR_EBREAKVU (1<<16)
#define DCSR_EBREAKM (1<<15)
#define DCSR_EBREAKH (1<<14)
#define DCSR_EBREAKS (1<<13)
#define DCSR_EBREAKU (1<<12)
#define DCSR_STOPCYCLE (1<<10)
#define DCSR_STEPIE (1<<11)
#define DCSR_STOPCOUNT (1<<10)
#define DCSR_STOPTIME (1<<9)
#define DCSR_CAUSE (7<<6)
#define DCSR_DEBUGINT (1<<5)
#define DCSR_HALT (1<<3)
#define DCSR_V (1<<5)
#define DCSR_MPRVEN (1<<4)
#define DCSR_NMIP (1<<3)
#define DCSR_STEP (1<<2)
#define DCSR_PRV (3<<0)

Expand Down Expand Up @@ -159,10 +166,12 @@
#define MENVCFG_CBIE 0x00000030
#define MENVCFG_CBCFE 0x00000040
#define MENVCFG_CBZE 0x00000080
#define MENVCFG_DTE 0x0800000000000000
#define MENVCFG_ADUE 0x2000000000000000
#define MENVCFG_PBMTE 0x4000000000000000
#define MENVCFG_STCE 0x8000000000000000

#define MENVCFGH_DTE 0x08000000
#define MENVCFGH_ADUE 0x20000000
#define MENVCFGH_PBMTE 0x40000000
#define MENVCFGH_STCE 0x80000000
Expand All @@ -172,11 +181,15 @@
#define MSTATEEN0_JVT 0x00000004
#define MSTATEEN0_PRIV114 0x0080000000000000
#define MSTATEEN0_HCONTEXT 0x0200000000000000
#define MSTATEEN0_AIA 0x0800000000000000
#define MSTATEEN0_CSRIND 0x1000000000000000
#define MSTATEEN0_HENVCFG 0x4000000000000000
#define MSTATEEN_HSTATEEN 0x8000000000000000

#define MSTATEEN0H_PRIV114 0x00800000
#define MSTATEEN0H_HCONTEXT 0x02000000
#define MSTATEEN0H_AIA 0x08000000
#define MSTATEEN0H_CSRIND 0x10000000
#define MSTATEEN0H_HENVCFG 0x40000000
#define MSTATEENH_HSTATEEN 0x80000000

Expand All @@ -200,10 +213,12 @@
#define HENVCFG_CBIE 0x00000030
#define HENVCFG_CBCFE 0x00000040
#define HENVCFG_CBZE 0x00000080
#define HENVCFG_DTE 0x0800000000000000
#define HENVCFG_ADUE 0x2000000000000000
#define HENVCFG_PBMTE 0x4000000000000000
#define HENVCFG_STCE 0x8000000000000000

#define HENVCFGH_DTE 0x08000000
#define HENVCFGH_ADUE 0x20000000
#define HENVCFGH_PBMTE 0x40000000
#define HENVCFGH_STCE 0x80000000
Expand All @@ -224,10 +239,14 @@
#define HSTATEEN0_FCSR 0x00000002
#define HSTATEEN0_JVT 0x00000004
#define HSTATEEN0_SCONTEXT 0x0200000000000000
#define HSTATEEN0_AIA 0x0800000000000000
#define HSTATEEN0_CSRIND 0x1000000000000000
#define HSTATEEN0_SENVCFG 0x4000000000000000
#define HSTATEEN_SSTATEEN 0x8000000000000000

#define HSTATEEN0H_SCONTEXT 0x02000000
#define HSTATEEN0H_AIA 0x08000000
#define HSTATEEN0H_CSRIND 0x10000000
#define HSTATEEN0H_SENVCFG 0x40000000
#define HSTATEENH_SSTATEEN 0x80000000

Expand Down Expand Up @@ -350,6 +369,7 @@

/* software check exception xtval codes */
#define LANDING_PAD_FAULT 2
#define SHADOW_STACK_FAULT 3

#ifdef __riscv

Expand Down
49 changes: 35 additions & 14 deletions parse.py
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Expand Up @@ -133,7 +133,7 @@ def process_enc_line(line, ext):

return (name, single_dict)

def same_base_ext (ext_name, ext_name_list):
def same_base_isa(ext_name, ext_name_list):
type1 = ext_name.split("_")[0]
for ext_name1 in ext_name_list:
type2 = ext_name1.split("_")[0]
Expand All @@ -144,6 +144,26 @@ def same_base_ext (ext_name, ext_name_list):
return True
return False

def overlaps(x, y):
x = x.rjust(len(y), '-')
y = y.rjust(len(x), '-')

for i in range(0, len(x)):
if not (x[i] == '-' or y[i] == '-' or x[i] == y[i]):
return False

return True

def overlap_allowed(a, x, y):
return x in a and y in a[x] or \
y in a and x in a[y]

def extension_overlap_allowed(x, y):
return overlap_allowed(overlapping_extensions, x, y)

def instruction_overlap_allowed(x, y):
return overlap_allowed(overlapping_instructions, x, y)

def create_inst_dict(file_filter, include_pseudo=False, include_pseudo_ops=[]):
'''
This function return a dictionary containing all instructions associated
Expand Down Expand Up @@ -222,29 +242,32 @@ def create_inst_dict(file_filter, include_pseudo=False, include_pseudo_ops=[]):
# instruction is already imported and raise SystemExit
if name in instr_dict:
var = instr_dict[name]["extension"]
if same_base_ext(ext_name, var):
# disable same names on the same base extensions
if same_base_isa(ext_name, var):
# disable same names on the same base ISA
err_msg = f'instruction : {name} from '
err_msg += f'{ext_name} is already '
err_msg += f'added from {var} in same base extensions'
err_msg += f'added from {var} in same base ISA'
logging.error(err_msg)
raise SystemExit(1)
elif instr_dict[name]['encoding'] != single_dict['encoding']:
# disable same names with different encodings on different base extensions
# disable same names with different encodings on different base ISAs
err_msg = f'instruction : {name} from '
err_msg += f'{ext_name} is already '
err_msg += f'added from {var} but each have different encodings in different base extensions'
err_msg += f'added from {var} but each have different encodings in different base ISAs'
logging.error(err_msg)
raise SystemExit(1)
instr_dict[name]['extension'].extend(single_dict['extension'])
else:
for key in instr_dict:
item = instr_dict[key]
if item["encoding"] == single_dict['encoding'] and same_base_ext(ext_name, item["extension"]):
# disable different names with same encodings on the same base extensions
err_msg = f'instruction : {name} from '
err_msg += f'{ext_name} has the same encoding with instruction {key} '
err_msg += f'added from {item["extension"]} in same base extensions'
if overlaps(item['encoding'], single_dict['encoding']) and \
not extension_overlap_allowed(ext_name, item['extension'][0]) and \
not instruction_overlap_allowed(name, key) and \
same_base_isa(ext_name, item['extension']):
# disable different names with overlapping encodings on the same base ISA
err_msg = f'instruction : {name} in extension '
err_msg += f'{ext_name} overlaps instruction {key} '
err_msg += f'in extension {item["extension"]}'
logging.error(err_msg)
raise SystemExit(1)

Expand Down Expand Up @@ -756,9 +779,7 @@ def make_chisel(instr_dict, spinal_hdl=False):
extensions = instr_dict_2_extensions(instr_dict)
for e in extensions:
e_instrs = filter(lambda i: instr_dict[i]['extension'][0] == e, instr_dict)
if "rv128_" in e:
e_format = e.replace("rv128_", "").upper() + "128"
elif "rv64_" in e:
if "rv64_" in e:
e_format = e.replace("rv64_", "").upper() + "64"
elif "rv32_" in e:
e_format = e.replace("rv32_", "").upper() + "32"
Expand Down
0 unratified/rv32_d_zfa → rv32_d_zfa
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2 changes: 1 addition & 1 deletion rv32_zbb
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@@ -1,3 +1,3 @@
$pseudo_op rv_zbe::pack zext.h.rv32 rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33
$pseudo_op rv_zbkb::pack zext.h.rv32 rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33
$pseudo_op rv64_zbp::grevi rev8.rv32 rd rs1 31..20=0x698 14..12=5 6..0=0x13
$pseudo_op rv64_zbb::rori rori.rv32 rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
0 unratified/rv64_q_zfa → rv64_q_zfa
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2 changes: 1 addition & 1 deletion rv64_zbb
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Expand Up @@ -5,5 +5,5 @@ rolw rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0E 1..0=
rorw rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0E 1..0=3
roriw rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x06 1..0=3
rori rd rs1 31..26=0x18 shamtd 14..12=5 6..2=0x04 1..0=3
$pseudo_op rv64_zbe::packw zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3
$pseudo_op rv64_zbkb::packw zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3
$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13
2 changes: 1 addition & 1 deletion rv64_zbkb
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Original file line number Diff line number Diff line change
Expand Up @@ -3,4 +3,4 @@ $import rv64_zbb::rolw
$import rv64_zbb::rorw
$import rv64_zbb::roriw
$import rv64_zbb::rori
$import rv64_zbe::packw
packw rd rs1 rs2 31..25=4 14..12=4 6..2=0x0E 1..0=3
2 changes: 1 addition & 1 deletion rv64_zk
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ $import rv64_zbb::rolw
$import rv64_zbb::rorw
$import rv64_zbb::roriw
$import rv64_zbb::rori
$import rv64_zbe::packw
$import rv64_zbkb::packw

#import zkne
# Scalar AES - RV64
Expand Down
2 changes: 1 addition & 1 deletion rv64_zkn
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ $import rv64_zbb::rolw
$import rv64_zbb::rorw
$import rv64_zbb::roriw
$import rv64_zbb::rori
$import rv64_zbe::packw
$import rv64_zbkb::packw

#import zkne
# Scalar AES - RV64
Expand Down
2 changes: 1 addition & 1 deletion rv64_zks
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Original file line number Diff line number Diff line change
Expand Up @@ -4,4 +4,4 @@ $import rv64_zbb::rolw
$import rv64_zbb::rorw
$import rv64_zbb::roriw
$import rv64_zbb::rori
$import rv64_zbe::packw
$import rv64_zbkb::packw
0 unratified/rv_c_zihintntl → rv_c_zihintntl
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0 unratified/rv_d_zfa → rv_d_zfa
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0 unratified/rv_f_zfa → rv_f_zfa
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0 unratified/rv_q_zfa → rv_q_zfa
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36 changes: 0 additions & 36 deletions rv_v
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Original file line number Diff line number Diff line change
Expand Up @@ -24,86 +24,50 @@ vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07
vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07
vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07
vle64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07
vle128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07
vle256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07
vle512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07
vle1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07
vse8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27
vse16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27
vse32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27
vse64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27
vse128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27
vse256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27
vse512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27
vse1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27

# Vector Indexed-Unordered Instructions (including segment part)
# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions
vluxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07
vluxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07
vluxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07
vluxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07
vluxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07
vluxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07
vluxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07
vluxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07
vsuxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
vsuxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
vsuxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
vsuxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
vsuxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
vsuxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
vsuxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
vsuxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27

# Vector Strided Instructions (including segment part)
# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#75-vector-strided-instructions
vlse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07
vlse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07
vlse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07
vlse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07
vlse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07
vlse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07
vlse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07
vlse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07
vsse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27
vsse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27
vsse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27
vsse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27
vsse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27
vsse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27
vsse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27
vsse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27

# Vector Indexed-Ordered Instructions (including segment part)
# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions
vloxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07
vloxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07
vloxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07
vloxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07
vloxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07
vloxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07
vloxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07
vloxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07
vsoxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
vsoxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
vsoxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
vsoxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
vsoxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
vsoxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
vsoxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
vsoxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27

# Unit-stride F31..29=0ault-Only-First Loads
# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#77-unit-stride-fault-only-first-loads
vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07
vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07
vle32ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07
vle64ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07
vle128ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07
vle256ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07
vle512ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07
vle1024ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07

# Vector Load/Store Whole Registers
# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions
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0 unratified/rv_zabha → rv_zabha
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4 changes: 2 additions & 2 deletions rv_zbkb
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Expand Up @@ -3,6 +3,6 @@ $import rv_zbb::ror
$import rv_zbb::andn
$import rv_zbb::orn
$import rv_zbb::xnor
$import rv_zbe::pack
$import rv_zbe::packh
pack rd rs1 rs2 31..25=4 14..12=4 6..2=0x0C 1..0=3
packh rd rs1 rs2 31..25=4 14..12=7 6..2=0x0C 1..0=3
$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3
4 changes: 2 additions & 2 deletions rv_zbkx
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@@ -1,2 +1,2 @@
$import rv_zbp::xperm4
$import rv_zbp::xperm8
xperm4 rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3
xperm8 rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3
0 unratified/rv_zcmop → rv_zcmop
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0 unratified/rv_zfh_zfa → rv_zfh_zfa
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0 unratified/rv_zicond → rv_zicond
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0 unratified/rv_zihintntl → rv_zihintntl
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0 unratified/rv_zimop → rv_zimop
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