Merge pull request #277 from foss-for-synopsys-dwc-arc-processors/Pse…

…udoinstructionsAdded Add some Pseudo Instructions from the ISA and ASM manual
riscv · Aug 23, 2024 · 290792c · 290792c
2 parents 41c6b4d + 62842a3
commit 290792c
Show file tree

Hide file tree

Showing 2 changed files with 27 additions and 0 deletions.
diff --git a/rv64_i b/rv64_i
@@ -18,3 +18,5 @@ subw    rd rs1 rs2 31..25=32 14..12=0 6..2=0x0E 1..0=3
 sllw    rd rs1 rs2 31..25=0  14..12=1 6..2=0x0E 1..0=3
 srlw    rd rs1 rs2 31..25=0  14..12=5 6..2=0x0E 1..0=3
 sraw    rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3
+
+$pseudo_op rv64_i::addiw sext.w rd rs1 31..20=0 14..12=0 6..2=0x06 1..0=3
diff --git a/rv_i b/rv_i
@@ -45,3 +45,28 @@ ebreak   31..20=0x001 19..7=0 6..2=0x1C 1..0=3
 $pseudo_op rv_i::ecall scall     11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3
 $pseudo_op rv_i::ebreak sbreak    11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3
 
+
+#pseudoinstructions from asm manual
+$pseudo_op rv_i::addi   mv rd rs1 31..20=0 14..12=0 6..2=0x04 1..0=3
+$pseudo_op rv_i::sub    neg rd rs1 31..25=32 24..20=0x0 14..12=0 6..2=0x0C 1..0=3
+$pseudo_op rv_i::addi   nop 31..20=0 19..15=0 14..12=0 11..7=0 6..2=0x04 1..0=3
+$pseudo_op rv_i::andi   zext.b rd rs1 31..20=0 14..12=7 6..2=0x04 1..0=3
+
+$pseudo_op rv_i::jalr ret 31..20=0 19..15=0x01 14..12=0 11..7=0 6..2=0x19 1..0=3
+
+$pseudo_op rv_i::bgeu   bleu bimm12hi rs2 rs1 bimm12lo 14..12=7 6..2=0x18 1..0=3
+$pseudo_op rv_i::bltu   bgtu bimm12hi rs2 rs1 bimm12lo 14..12=6 6..2=0x18 1..0=3
+$pseudo_op rv_i::bge    ble  bimm12hi rs2 rs1 bimm12lo 14..12=5 6..2=0x18 1..0=3
+$pseudo_op rv_i::bge    bgez bimm12hi rs1     bimm12lo 24..20=0x0 14..12=5 6..2=0x18 1..0=3
+$pseudo_op rv_i::bge    blez bimm12hi rs2     bimm12lo 19..15=0x0 14..12=5 6..2=0x18 1..0=3
+$pseudo_op rv_i::blt    bgt  bimm12hi rs2 rs1 bimm12lo 14..12=4 6..2=0x18 1..0=3
+$pseudo_op rv_i::blt    bgtz bimm12hi rs2     bimm12lo 19..15=0x0 14..12=4 6..2=0x18 1..0=3
+$pseudo_op rv_i::blt    bltz bimm12hi rs1     bimm12lo 24..20=0x0 14..12=4 6..2=0x18 1..0=3
+$pseudo_op rv_i::bne    bnez bimm12hi rs1     bimm12lo 24..20=0x0 14..12=1 6..2=0x18 1..0=3
+$pseudo_op rv_i::beq    beqz bimm12hi rs1     bimm12lo 24..20=0x0 14..12=0 6..2=0x18 1..0=3
+
+$pseudo_op rv_i::sltiu  seqz rd rs1 31..20=1 14..12=3 6..2=0x04 1..0=3
+$pseudo_op rv_i::sltu   snez rd rs2 31..25=0 19..15=0x0 14..12=3 6..2=0x0C 1..0=3
+$pseudo_op rv_i::slt    sltz rd rs1 31..25=0 24..20=0x0 14..12=2 6..2=0x0C 1..0=3
+$pseudo_op rv_i::slt    sgtz rd rs2 31..25=0 19..15=0x0 14..12=2 6..2=0x0C 1..0=3
+