add srmcfg CSR

riscv · Dec 23, 2023 · d5f2867 · d5f2867
1 parent 61d2ef4
commit d5f2867
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diff --git a/csrs.csv b/csrs.csv
@@ -70,6 +70,7 @@
 0x157, "sireg6"
 0x15C, "stopei"
 0x180, "satp"
+0x181, "srmcfg"
 0x5A8, "scontext"
 0x200, "vsstatus"
 0x204, "vsie"

diff --git a/encoding.h b/encoding.h
@@ -330,6 +330,10 @@
 
 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
 
+/* srmcfg CSR fields */
+#define SRMCFG_RCID  0x00000FFF
+#define SRMCFG_MCID  0x0FFF0000
+
 #ifdef __riscv
 
 #if __riscv_xlen == 64