Added Pseudo-instructions from F and D. Allow for instructions to have a special field.

[AFOliveira]

This time there was a need to modify parse.py a tiny bit in order to fully accommodate all pseudo-instructions.
Since parse.py did not allow to have pseudoinstructions with the two of the same register(e.g. fmv_s rs, rs) due to how it parses, I created a work around, that I succesfully checked does not break any of the pre-existing instructions. It allows that a register is equalled to anything, as in, "rs2=rs1" and uses the "rs2" to know it's position in encoding.

Adittionally, I added the following pseudo-instructions:

F

fmv.s
fabs.s
fneg.s

D

fmv.d
fabs.d
fneg.d

[aswaterman]

To keep things symmetric, can you add the analogous pseudoinstructions for Zfh and Q, too?

[AFOliveira]

Sorry to get back on this but I'm actually having a hard time finding "Zfh" and ''Q'' pseudo-instructions since I believe they aren't in the ASM Manual and I also could not find them in the ISA spec, is there somewhere you can point me to so I can indeed add them here?

[aswaterman]

It's possible that someone forgot to update the asm manual, but Zfh and Q have exactly analogous pseudoinstructions (fmv.h, fabs.h, fneg.h; fmv.q, fabs.q, fneg.q). Binutils implements them, for example. We should include them here, this repo being the source of truth, then update the asm manual accordingly.

https://github.com/bminor/binutils-gdb/blob/2e9df7573a1a7df1c34321c0837eb46b2be5d4a5/opcodes/riscv-opc.c#L815-L817

https://github.com/bminor/binutils-gdb/blob/2e9df7573a1a7df1c34321c0837eb46b2be5d4a5/opcodes/riscv-opc.c#L1022-L1024

[AFOliveira]

Thank you for clarifying and linking the binutils! Latest commit should address all of this.

[AFOliveira]

All should now be solved. Sorry for the mess and the copy-paste error.

[aswaterman]

@AFOliveira no prob, that's what code review is for!