Add RV32 restriction for compressed shift instructions · riscv/sail-riscv@d6ff4ee

Triggered via pull request March 19, 2024 09:50

opened #440

Status Success

Total duration 24m 21s

Artifacts 2

compile.yml

on: pull_request

1 notice

There are 712 tests, see "Raw output" for the full list of tests.

Produced during runtime

Name	Size
event.json Expired	3.47 KB
tests.xml Expired	2.82 KB