Merge branch 'riscv:master' into pmm_support

riscv · Apr 26, 2024 · 1ceb4a1 · 1ceb4a1
2 parents 717cb55 + 495b52c
commit 1ceb4a1
Show file tree

Hide file tree

Showing 5 changed files with 9 additions and 4 deletions.
diff --git a/model/riscv_csr_map.sail b/model/riscv_csr_map.sail
@@ -58,6 +58,7 @@ mapping clause csr_name_map = 0xF11  <-> "mvendorid"
 mapping clause csr_name_map = 0xF12  <-> "marchid"
 mapping clause csr_name_map = 0xF13  <-> "mimpid"
 mapping clause csr_name_map = 0xF14  <-> "mhartid"
+mapping clause csr_name_map = 0xF15  <-> "mconfigptr"
 /* machine trap setup */
 mapping clause csr_name_map = 0x300  <-> "mstatus"
 mapping clause csr_name_map = 0x301  <-> "misa"

diff --git a/model/riscv_insts_dext.sail b/model/riscv_insts_dext.sail
@@ -902,11 +902,11 @@ mapping clause encdec = F_UN_TYPE_D(rs1, rd, FCLASS_D)                        if
 
 /* D instructions, RV64 only */
 
-mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_X_D)                         if haveDExt()
-                    <-> 0b111_0001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011  if haveDExt()
+mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_X_D)                         if haveDExt() & sizeof(xlen) >= 64
+                    <-> 0b111_0001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011  if haveDExt() & sizeof(xlen) >= 64
 
-mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_D_X)                         if haveDExt()
-                    <-> 0b111_1001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011  if haveDExt()
+mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_D_X)                         if haveDExt() & sizeof(xlen) >= 64
+                    <-> 0b111_1001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011  if haveDExt() & sizeof(xlen) >= 64
 
 /* Execution semantics ================================ */
 

diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
@@ -29,6 +29,7 @@ function readCSR csr : csreg -> xlenbits = {
     (0xF12,  _) => marchid,
     (0xF13,  _) => mimpid,
     (0xF14,  _) => mhartid,
+    (0xF15,  _) => mconfigptr,
     (0x300,  _) => mstatus.bits,
     (0x301,  _) => misa.bits,
     (0x302,  _) => medeleg.bits,

diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
@@ -21,6 +21,7 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool =
     0xf12 => p == Machine, // marchdid
     0xf13 => p == Machine, // mimpid
     0xf14 => p == Machine, // mhartid
+    0xf15 => p == Machine, // mconfigptr
     /* machine mode: trap setup */
     0x300 => p == Machine, // mstatus
     0x301 => p == Machine, // misa
@@ -481,6 +482,7 @@ function init_sys() -> unit = {
   cur_privilege = Machine;
 
   mhartid     = zero_extend(0b0);
+  mconfigptr  = zero_extend(0b0);
 
   misa[MXL] = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64);
   misa[A]   = 0b1;                             /* atomics */

diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
@@ -517,6 +517,7 @@ register mimpid : xlenbits
 register marchid : xlenbits
 /* TODO: this should be readonly, and always 0 for now */
 register mhartid : xlenbits
+register mconfigptr : xlenbits
 
 /* S-mode registers */