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Softfloat: Add soft floating-point equals API in sail model
This patch would like to introduce the soft floating-point equals API into the sail model. Then the softfloat_interface is able to leverage the new softfloat in sail, instead of the c_emulator. * Add softfloat common for softfloat enter and leave. * Add enum like immutable exception flags. * Add softfloat equals API for half, single and double floating-point. * Replace the extern call of softfloat interface to sail model. * Add helper functions to utils. * Adjust build system for new files. Signed-off-by: Pan Li <pan2.li@intel.com>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,123 @@ | ||
| /*=======================================================================================*/ | ||
| /* RISCV Sail Model */ | ||
| /* */ | ||
| /* This Sail RISC-V architecture model, comprising all files and */ | ||
| /* directories except for the snapshots of the Lem and Sail libraries */ | ||
| /* in the prover_snapshots directory (which include copies of their */ | ||
| /* licences), is subject to the BSD two-clause licence below. */ | ||
| /* */ | ||
| /* Copyright (c) 2017-2023 */ | ||
| /* Prashanth Mundkur */ | ||
| /* Rishiyur S. Nikhil and Bluespec, Inc. */ | ||
| /* Jon French */ | ||
| /* Brian Campbell */ | ||
| /* Robert Norton-Wright */ | ||
| /* Alasdair Armstrong */ | ||
| /* Thomas Bauereiss */ | ||
| /* Shaked Flur */ | ||
| /* Christopher Pulte */ | ||
| /* Peter Sewell */ | ||
| /* Alexander Richardson */ | ||
| /* Hesham Almatary */ | ||
| /* Jessica Clarke */ | ||
| /* Microsoft, for contributions by Robert Norton-Wright and Nathaniel Wesley Filardo */ | ||
| /* Intel, for contributions by Pan Li */ | ||
| /* Peter Rugg */ | ||
| /* Aril Computer Corp., for contributions by Scott Johnson */ | ||
| /* Philipp Tomsich */ | ||
| /* VRULL GmbH, for contributions by its employees */ | ||
| /* */ | ||
| /* All rights reserved. */ | ||
| /* */ | ||
| /* This software was developed by the above within the Rigorous */ | ||
| /* Engineering of Mainstream Systems (REMS) project, partly funded by */ | ||
| /* EPSRC grant EP/K008528/1, at the Universities of Cambridge and */ | ||
| /* Edinburgh. */ | ||
| /* */ | ||
| /* This software was developed by SRI International and the University of */ | ||
| /* Cambridge Computer Laboratory (Department of Computer Science and */ | ||
| /* Technology) under DARPA/AFRL contract FA8650-18-C-7809 ("CIFV"), and */ | ||
| /* under DARPA contract HR0011-18-C-0016 ("ECATS") as part of the DARPA */ | ||
| /* SSITH research programme. */ | ||
| /* */ | ||
| /* This project has received funding from the European Research Council */ | ||
| /* (ERC) under the European Union’s Horizon 2020 research and innovation */ | ||
| /* programme (grant agreement 789108, ELVER). */ | ||
| /* */ | ||
| /* */ | ||
| /* Redistribution and use in source and binary forms, with or without */ | ||
| /* modification, are permitted provided that the following conditions */ | ||
| /* are met: */ | ||
| /* 1. Redistributions of source code must retain the above copyright */ | ||
| /* notice, this list of conditions and the following disclaimer. */ | ||
| /* 2. Redistributions in binary form must reproduce the above copyright */ | ||
| /* notice, this list of conditions and the following disclaimer in */ | ||
| /* the documentation and/or other materials provided with the */ | ||
| /* distribution. */ | ||
| /* */ | ||
| /* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ | ||
| /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ | ||
| /* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ | ||
| /* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ | ||
| /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ | ||
| /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ | ||
| /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ | ||
| /* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ | ||
| /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ | ||
| /* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ | ||
| /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ | ||
| /* SUCH DAMAGE. */ | ||
| /*=======================================================================================*/ | ||
|
|
||
| /* **************************************************************** */ | ||
| /* This file implements the floating-point for some common helper */ | ||
| /* functions. They will be leveraged by other softfloat sail */ | ||
| /* implementations. */ | ||
| /* */ | ||
| /* However, the implementation still need some global variables in */ | ||
| /* file riscv_softfloat_interface.sail. It includes: */ | ||
| /* 1. float_result. */ | ||
| /* 2. float_fflags. */ | ||
| /* 3. float_roundingMode. */ | ||
| /* **************************************************************** */ | ||
|
|
||
| let softfloat_flag_inexact : bits(64) = 0x0000000000000001 | ||
| let softfloat_flag_underflow : bits(64) = 0x0000000000000002 | ||
| let softfloat_flag_overflow : bits(64) = 0x0000000000000004 | ||
| let softfloat_flag_infinit : bits(64) = 0x0000000000000008 | ||
| let softfloat_flag_invalid : bits(64) = 0x0000000000000010 | ||
|
|
||
| val riscv_softfloat_enter : (bits_rm) -> unit | ||
| function riscv_softfloat_enter (roundingMode) -> unit = { | ||
| float_fflags = zeros(64); | ||
| float_roundingMode = roundingMode; | ||
| } | ||
|
|
||
| val riscv_softfloat_bits_H_leave : (bits_H) -> unit | ||
| function riscv_softfloat_bits_H_leave (result) -> unit = { | ||
| float_result[15 .. 0] = result; | ||
| } | ||
|
|
||
| val riscv_softfloat_bits_S_leave : (bits_S) -> unit | ||
| function riscv_softfloat_bits_S_leave (result) -> unit = { | ||
| float_result[31 .. 0] = result; | ||
| } | ||
|
|
||
| val riscv_softfloat_bits_D_leave : (bits_D) -> unit | ||
| function riscv_softfloat_bits_D_leave (result) -> unit = { | ||
| float_result[63 .. 0] = result; | ||
| } | ||
|
|
||
| val riscv_softfloat_leave : forall 'm, 'm in {16, 32, 64}. bits('m) -> unit | ||
| function riscv_softfloat_leave (op) = { | ||
| match 'm { | ||
| 16 => riscv_softfloat_bits_H_leave(op), | ||
| 32 => riscv_softfloat_bits_S_leave(op), | ||
| 64 => riscv_softfloat_bits_D_leave(op), | ||
| } | ||
| } | ||
|
|
||
| val riscv_softfloat_raise_flags : (bits(64)) -> unit | ||
| function riscv_softfloat_raise_flags (flags) -> unit = { | ||
| float_fflags = float_fflags | flags | ||
| } |
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