add blanks

riscv · Nov 26, 2023 · 34e9f45 · 34e9f45
1 parent fc0b599
commit 34e9f45
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
@@ -634,8 +634,8 @@ bitfield Sstatus : xlenbits = {
   SIE  : 1,
   UIE  : 0
 }
-
 /* sstatus is a view of mstatus, so there is no register defined. */
+
 function get_sstatus_UXL(s : Sstatus) -> arch_xlen = {
   let m = Mk_Mstatus(s.bits());
   get_mstatus_UXL(m)