add a Sstc test

riscv · Jan 22, 2024 · 3cd923a · 3cd923a
1 parent 1e20dc8
commit 3cd923a
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
@@ -420,7 +420,7 @@ function legalize_mip(o : Minterrupts, v : xlenbits) -> Minterrupts = {
    * extension, the U-mode bits. */
   let v = Mk_Minterrupts(v);
   let m = update_SEI(o, v.SEI());
-  let m = if ( not(haveSstc()) | (haveSstc() & (menvcfg.STCE() == 0b0)) ) then {
+  let m = if ( not(haveSstc()) | menvcfg.STCE() == 0b0 ) then {
     update_STI(m, v.STI());
   } else m;
   let m = update_SSI(m, v.SSI());
@@ -745,7 +745,7 @@ function lower_mie(m : Minterrupts, d : Minterrupts) -> Sinterrupts = {
 function lift_sip(o : Minterrupts, d : Minterrupts, s : Sinterrupts) -> Minterrupts = {
   let m : Minterrupts = o;
   let m = if d.SSI() == 0b1 then update_SSI(m, s.SSI()) else m;
-  let m = if d.STI() == 0b1 & (not(haveSstc()) | (haveSstc() & menvcfg.STCE() == 0b0)) then {
+  let m = if d.STI() == 0b1 & (not(haveSstc()) | menvcfg.STCE() == 0b0) then {
     update_STI(m, s.STI());
   } else m;
   if haveNExt() then {

diff --git a/test/riscv-tests/rv64si-p-stimecmp.elf b/test/riscv-tests/rv64si-p-stimecmp.elf