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Add enums and "extensionEnabled" function for discriminating extensio…
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Extensions: D, F, Zbc, Zbkb, Zbkc, Zbkx, Zbs, Zfa, Zfh, Zicond, Zknd,
Zkne, Zknh, Zkr, Zksed, Zksh.
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@ThinkOpenly
ThinkOpenly committed Jul 9, 2024
1 parent b6cdb53 commit 3d26904
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Showing 19 changed files with 272 additions and 245 deletions.
12 changes: 9 additions & 3 deletions model/riscv_fdext_control.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -15,11 +15,17 @@

/* **************************************************************** */

enum clause extensions = Ext_F
function clause extensionEnabled(Ext_F) = (misa[F] == 0b1) & (mstatus[FS] != 0b00)

enum clause extensions = Ext_D
function clause extensionEnabled(Ext_D) = (misa[D] == 0b1) & (mstatus[FS] != 0b00) & sizeof(flen) >= 64

/* val clause ext_is_CSR_defined : (csreg, Privilege) -> bool */

function clause ext_is_CSR_defined (0x001, _) = haveFExt() | haveZfinx()
function clause ext_is_CSR_defined (0x002, _) = haveFExt() | haveZfinx()
function clause ext_is_CSR_defined (0x003, _) = haveFExt() | haveZfinx()
function clause ext_is_CSR_defined (0x001, _) = extensionEnabled(Ext_F) | haveZfinx()
function clause ext_is_CSR_defined (0x002, _) = extensionEnabled(Ext_F) | haveZfinx()
function clause ext_is_CSR_defined (0x003, _) = extensionEnabled(Ext_F) | haveZfinx()

function clause ext_read_CSR (0x001) = Some(zero_extend(fcsr[FFLAGS]))
function clause ext_read_CSR (0x002) = Some(zero_extend(fcsr[FRM]))
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16 changes: 8 additions & 8 deletions model/riscv_insts_cdext.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -17,9 +17,9 @@
union clause ast = C_FLDSP : (bits(6), regidx)

mapping clause encdec_compressed = C_FLDSP(ui86 @ ui5 @ ui43, rd)
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & extensionEnabled(Ext_D)
<-> 0b001 @ ui5 : bits(1) @ rd : regidx @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & extensionEnabled(Ext_D)

function clause execute (C_FLDSP(uimm, rd)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
Expand All @@ -35,9 +35,9 @@ mapping clause assembly = C_FLDSP(uimm, rd)
union clause ast = C_FSDSP : (bits(6), regidx)

mapping clause encdec_compressed = C_FSDSP(ui86 @ ui53, rs2)
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & extensionEnabled(Ext_D)
<-> 0b101 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regidx @ 0b10
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & extensionEnabled(Ext_D)

function clause execute (C_FSDSP(uimm, rs2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
Expand All @@ -53,9 +53,9 @@ mapping clause assembly = C_FSDSP(uimm, rs2)
union clause ast = C_FLD : (bits(5), cregidx, cregidx)

mapping clause encdec_compressed = C_FLD(ui76 @ ui53, rs1, rd)
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & extensionEnabled(Ext_D)
<-> 0b001 @ ui53 : bits(3) @ rs1 : cregidx @ ui76 : bits(2) @ rd : cregidx @ 0b00
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & extensionEnabled(Ext_D)

function clause execute (C_FLD(uimm, rsc, rdc)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
Expand All @@ -73,9 +73,9 @@ mapping clause assembly = C_FLD(uimm, rsc, rdc)
union clause ast = C_FSD : (bits(5), cregidx, cregidx)

mapping clause encdec_compressed = C_FSD(ui76 @ ui53, rs1, rs2)
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & extensionEnabled(Ext_D)
<-> 0b101 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & extensionEnabled(Ext_D)

function clause execute (C_FSD(uimm, rsc1, rsc2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
Expand Down
16 changes: 8 additions & 8 deletions model/riscv_insts_cfext.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -17,9 +17,9 @@
union clause ast = C_FLWSP : (bits(6), regidx)

mapping clause encdec_compressed = C_FLWSP(ui76 @ ui5 @ ui42, rd)
if sizeof(xlen) == 32 & haveRVC() & haveFExt()
if sizeof(xlen) == 32 & haveRVC() & extensionEnabled(Ext_F)
<-> 0b011 @ ui5 : bits(1) @ rd : regidx @ ui42 : bits(3) @ ui76 : bits(2) @ 0b10
if sizeof(xlen) == 32 & haveRVC() & haveFExt()
if sizeof(xlen) == 32 & haveRVC() & extensionEnabled(Ext_F)

function clause execute (C_FLWSP(imm, rd)) = {
let imm : bits(12) = zero_extend(imm @ 0b00);
Expand All @@ -35,9 +35,9 @@ mapping clause assembly = C_FLWSP(imm, rd)
union clause ast = C_FSWSP : (bits(6), regidx)

mapping clause encdec_compressed = C_FSWSP(ui76 @ ui52, rs2)
if sizeof(xlen) == 32 & haveRVC() & haveFExt()
if sizeof(xlen) == 32 & haveRVC() & extensionEnabled(Ext_F)
<-> 0b111 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regidx @ 0b10
if sizeof(xlen) == 32 & haveRVC() & haveFExt()
if sizeof(xlen) == 32 & haveRVC() & extensionEnabled(Ext_F)

function clause execute (C_FSWSP(uimm, rs2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
Expand All @@ -53,9 +53,9 @@ mapping clause assembly = C_FSWSP(uimm, rs2)
union clause ast = C_FLW : (bits(5), cregidx, cregidx)

mapping clause encdec_compressed = C_FLW(ui6 @ ui53 @ ui2, rs1, rd)
if sizeof(xlen) == 32 & haveRVC() & haveFExt()
if sizeof(xlen) == 32 & haveRVC() & extensionEnabled(Ext_F)
<-> 0b011 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregidx @ 0b00
if sizeof(xlen) == 32 & haveRVC() & haveFExt()
if sizeof(xlen) == 32 & haveRVC() & extensionEnabled(Ext_F)

function clause execute (C_FLW(uimm, rsc, rdc)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
Expand All @@ -73,9 +73,9 @@ mapping clause assembly = C_FLW(uimm, rsc, rdc)
union clause ast = C_FSW : (bits(5), cregidx, cregidx)

mapping clause encdec_compressed = C_FSW(ui6 @ ui53 @ ui2, rs1, rs2)
if sizeof(xlen) == 32 & haveRVC() & haveFExt()
if sizeof(xlen) == 32 & haveRVC() & extensionEnabled(Ext_F)
<-> 0b111 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregidx @ 0b00
if sizeof(xlen) == 32 & haveRVC() & haveFExt()
if sizeof(xlen) == 32 & haveRVC() & extensionEnabled(Ext_F)

function clause execute (C_FSW(uimm, rsc1, rsc2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
Expand Down
10 changes: 5 additions & 5 deletions model/riscv_insts_dext.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -224,7 +224,7 @@ function fle_D (v1, v2, is_quiet) = {
/* **************************************************************** */
/* Helper functions for 'encdec()' */

function haveDoubleFPU() -> bool = haveDExt() | haveZdinx()
function haveDoubleFPU() -> bool = extensionEnabled(Ext_D) | haveZdinx()

/* RV32Zdinx requires even register pairs; can be omitted for code */
/* not used for RV32Zdinx (i.e. RV64-only or D-only). */
Expand Down Expand Up @@ -902,11 +902,11 @@ mapping clause encdec = F_UN_TYPE_D(rs1, rd, FCLASS_D) if

/* D instructions, RV64 only */

mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_X_D) if haveDExt() & sizeof(xlen) >= 64
<-> 0b111_0001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveDExt() & sizeof(xlen) >= 64
mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_X_D) if extensionEnabled(Ext_D) & sizeof(xlen) >= 64
<-> 0b111_0001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_D) & sizeof(xlen) >= 64

mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_D_X) if haveDExt() & sizeof(xlen) >= 64
<-> 0b111_1001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveDExt() & sizeof(xlen) >= 64
mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_D_X) if extensionEnabled(Ext_D) & sizeof(xlen) >= 64
<-> 0b111_1001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_D) & sizeof(xlen) >= 64

/* Execution semantics ================================ */

Expand Down
2 changes: 2 additions & 0 deletions model/riscv_insts_end.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,8 @@ mapping clause assembly = C_ILLEGAL(s) <-> "c.illegal" ^ spc() ^ hex_bits_16(s)
/* ****************************************************************** */

/* End definitions */
end extension_supported
end extensions
end ast
end execute
end assembly
Expand Down
37 changes: 20 additions & 17 deletions model/riscv_insts_fext.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,9 @@

/* **************************************************************** */

enum clause extensions = Ext_Zfh
function clause extensionEnabled(Ext_Zfh) = (misa[F] == 0b1) & (mstatus[FS] != 0b00)

mapping encdec_rounding_mode : rounding_mode <-> bits(3) = {
RM_RNE <-> 0b000,
RM_RTZ <-> 0b001,
Expand Down Expand Up @@ -259,7 +262,7 @@ function fle_S (v1, v2, is_quiet) = {
/* **************************************************************** */
/* Helper functions for 'encdec()' */

function haveSingleFPU() -> bool = haveFExt() | haveZfinx()
function haveSingleFPU() -> bool = extensionEnabled(Ext_F) | haveZfinx()

/* ****************************************************************** */
/* Floating-point loads */
Expand All @@ -271,14 +274,14 @@ union clause ast = LOAD_FP : (bits(12), regidx, regidx, word_width)

/* AST <-> Binary encoding ================================ */

mapping clause encdec = LOAD_FP(imm, rs1, rd, HALF) if haveZfh()
<-> imm @ rs1 @ 0b001 @ rd @ 0b000_0111 if haveZfh()
mapping clause encdec = LOAD_FP(imm, rs1, rd, HALF) if extensionEnabled(Ext_Zfh)
<-> imm @ rs1 @ 0b001 @ rd @ 0b000_0111 if extensionEnabled(Ext_Zfh)

mapping clause encdec = LOAD_FP(imm, rs1, rd, WORD) if haveFExt()
<-> imm @ rs1 @ 0b010 @ rd @ 0b000_0111 if haveFExt()
mapping clause encdec = LOAD_FP(imm, rs1, rd, WORD) if extensionEnabled(Ext_F)
<-> imm @ rs1 @ 0b010 @ rd @ 0b000_0111 if extensionEnabled(Ext_F)

mapping clause encdec = LOAD_FP(imm, rs1, rd, DOUBLE) if haveDExt()
<-> imm @ rs1 @ 0b011 @ rd @ 0b000_0111 if haveDExt()
mapping clause encdec = LOAD_FP(imm, rs1, rd, DOUBLE) if extensionEnabled(Ext_D)
<-> imm @ rs1 @ 0b011 @ rd @ 0b000_0111 if extensionEnabled(Ext_D)

/* Execution semantics ================================ */

Expand Down Expand Up @@ -357,14 +360,14 @@ union clause ast = STORE_FP : (bits(12), regidx, regidx, word_width)

/* AST <-> Binary encoding ================================ */

mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, HALF) if haveZfh()
<-> imm7 : bits(7) @ rs2 @ rs1 @ 0b001 @ imm5 : bits(5) @ 0b010_0111 if haveZfh()
mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, HALF) if extensionEnabled(Ext_Zfh)
<-> imm7 : bits(7) @ rs2 @ rs1 @ 0b001 @ imm5 : bits(5) @ 0b010_0111 if extensionEnabled(Ext_Zfh)

mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, WORD) if haveFExt()
<-> imm7 : bits(7) @ rs2 @ rs1 @ 0b010 @ imm5 : bits(5) @ 0b010_0111 if haveFExt()
mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, WORD) if extensionEnabled(Ext_F)
<-> imm7 : bits(7) @ rs2 @ rs1 @ 0b010 @ imm5 : bits(5) @ 0b010_0111 if extensionEnabled(Ext_F)

mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, DOUBLE) if haveDExt()
<-> imm7 : bits(7) @ rs2 @ rs1 @ 0b011 @ imm5 : bits(5) @ 0b010_0111 if haveDExt()
mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, DOUBLE) if extensionEnabled(Ext_D)
<-> imm7 : bits(7) @ rs2 @ rs1 @ 0b011 @ imm5 : bits(5) @ 0b010_0111 if extensionEnabled(Ext_D)

/* Execution semantics ================================ */

Expand Down Expand Up @@ -1024,11 +1027,11 @@ union clause ast = F_UN_TYPE_S : (regidx, regidx, f_un_op_S)
mapping clause encdec = F_UN_TYPE_S(rs1, rd, FCLASS_S) if haveSingleFPU()
<-> 0b111_0000 @ 0b00000 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveSingleFPU()

mapping clause encdec = F_UN_TYPE_S(rs1, rd, FMV_X_W) if haveFExt()
<-> 0b111_0000 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveFExt()
mapping clause encdec = F_UN_TYPE_S(rs1, rd, FMV_X_W) if extensionEnabled(Ext_F)
<-> 0b111_0000 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_F)

mapping clause encdec = F_UN_TYPE_S(rs1, rd, FMV_W_X) if haveFExt()
<-> 0b111_1000 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveFExt()
mapping clause encdec = F_UN_TYPE_S(rs1, rd, FMV_W_X) if extensionEnabled(Ext_F)
<-> 0b111_1000 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_F)

/* Execution semantics ================================ */

Expand Down
47 changes: 25 additions & 22 deletions model/riscv_insts_zbb.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -6,11 +6,14 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extensions = Ext_Zbkb
function clause extensionEnabled(Ext_Zbkb) = true

/* ****************************************************************** */
union clause ast = RISCV_RORIW : (bits(5), regidx, regidx)

mapping clause encdec = RISCV_RORIW(shamt, rs1, rd) if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64
<-> 0b0110000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011 if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64
mapping clause encdec = RISCV_RORIW(shamt, rs1, rd) if (haveZbb() | extensionEnabled(Ext_Zbkb)) & sizeof(xlen) == 64
<-> 0b0110000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011 if (haveZbb() | extensionEnabled(Ext_Zbkb)) & sizeof(xlen) == 64

mapping clause assembly = RISCV_RORIW(shamt, rs1, rd)
<-> "roriw" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_5(shamt)
Expand All @@ -25,8 +28,8 @@ function clause execute (RISCV_RORIW(shamt, rs1, rd)) = {
/* ****************************************************************** */
union clause ast = RISCV_RORI : (bits(6), regidx, regidx)

mapping clause encdec = RISCV_RORI(shamt, rs1, rd) if (haveZbb() | haveZbkb()) & (sizeof(xlen) == 64 | shamt[5] == bitzero)
<-> 0b011000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if (haveZbb() | haveZbkb()) & (sizeof(xlen) == 64 | shamt[5] == bitzero)
mapping clause encdec = RISCV_RORI(shamt, rs1, rd) if (haveZbb() | extensionEnabled(Ext_Zbkb)) & (sizeof(xlen) == 64 | shamt[5] == bitzero)
<-> 0b011000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if (haveZbb() | extensionEnabled(Ext_Zbkb)) & (sizeof(xlen) == 64 | shamt[5] == bitzero)

mapping clause assembly = RISCV_RORI(shamt, rs1, rd)
<-> "rori" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_6(shamt)
Expand All @@ -43,11 +46,11 @@ function clause execute (RISCV_RORI(shamt, rs1, rd)) = {
/* ****************************************************************** */
union clause ast = ZBB_RTYPEW : (regidx, regidx, regidx, bropw_zbb)

mapping clause encdec = ZBB_RTYPEW(rs2, rs1, rd, RISCV_ROLW) if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64
<-> 0b0110000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0111011 if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64
mapping clause encdec = ZBB_RTYPEW(rs2, rs1, rd, RISCV_ROLW) if (haveZbb() | extensionEnabled(Ext_Zbkb)) & sizeof(xlen) == 64
<-> 0b0110000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0111011 if (haveZbb() | extensionEnabled(Ext_Zbkb)) & sizeof(xlen) == 64

mapping clause encdec = ZBB_RTYPEW(rs2, rs1, rd, RISCV_RORW) if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64
<-> 0b0110000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011 if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64
mapping clause encdec = ZBB_RTYPEW(rs2, rs1, rd, RISCV_RORW) if (haveZbb() | extensionEnabled(Ext_Zbkb)) & sizeof(xlen) == 64
<-> 0b0110000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011 if (haveZbb() | extensionEnabled(Ext_Zbkb)) & sizeof(xlen) == 64

mapping zbb_rtypew_mnemonic : bropw_zbb <-> string = {
RISCV_ROLW <-> "rolw",
Expand All @@ -71,14 +74,14 @@ function clause execute (ZBB_RTYPEW(rs2, rs1, rd, op)) = {
/* ****************************************************************** */
union clause ast = ZBB_RTYPE : (regidx, regidx, regidx, brop_zbb)

mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ANDN) if haveZbb() | haveZbkb()
<-> 0b0100000 @ rs2 @ rs1 @ 0b111 @ rd @ 0b0110011 if haveZbb() | haveZbkb()
mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ANDN) if haveZbb() | extensionEnabled(Ext_Zbkb)
<-> 0b0100000 @ rs2 @ rs1 @ 0b111 @ rd @ 0b0110011 if haveZbb() | extensionEnabled(Ext_Zbkb)

mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ORN) if haveZbb() | haveZbkb()
<-> 0b0100000 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0110011 if haveZbb() | haveZbkb()
mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ORN) if haveZbb() | extensionEnabled(Ext_Zbkb)
<-> 0b0100000 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0110011 if haveZbb() | extensionEnabled(Ext_Zbkb)

mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_XNOR) if haveZbb() | haveZbkb()
<-> 0b0100000 @ rs2 @ rs1 @ 0b100 @ rd @ 0b0110011 if haveZbb() | haveZbkb()
mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_XNOR) if haveZbb() | extensionEnabled(Ext_Zbkb)
<-> 0b0100000 @ rs2 @ rs1 @ 0b100 @ rd @ 0b0110011 if haveZbb() | extensionEnabled(Ext_Zbkb)

mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_MAX) if haveZbb()
<-> 0b0000101 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0110011 if haveZbb()
Expand All @@ -92,11 +95,11 @@ mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_MIN) if haveZbb()
mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_MINU) if haveZbb()
<-> 0b0000101 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011 if haveZbb()

mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ROL) if haveZbb() | haveZbkb()
<-> 0b0110000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011 if haveZbb() | haveZbkb()
mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ROL) if haveZbb() | extensionEnabled(Ext_Zbkb)
<-> 0b0110000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011 if haveZbb() | extensionEnabled(Ext_Zbkb)

mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ROR) if haveZbb() | haveZbkb()
<-> 0b0110000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011 if haveZbb() | haveZbkb()
mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ROR) if haveZbb() | extensionEnabled(Ext_Zbkb)
<-> 0b0110000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011 if haveZbb() | extensionEnabled(Ext_Zbkb)

mapping zbb_rtype_mnemonic : brop_zbb <-> string = {
RISCV_ANDN <-> "andn",
Expand Down Expand Up @@ -173,11 +176,11 @@ function clause execute (ZBB_EXTOP(rs1, rd, op)) = {
/* ****************************************************************** */
union clause ast = RISCV_REV8 : (regidx, regidx)

mapping clause encdec = RISCV_REV8(rs1, rd) if (haveZbb() | haveZbkb()) & sizeof(xlen) == 32
<-> 0b011010011000 @ rs1 @ 0b101 @ rd @ 0b0010011 if (haveZbb() | haveZbkb()) & sizeof(xlen) == 32
mapping clause encdec = RISCV_REV8(rs1, rd) if (haveZbb() | extensionEnabled(Ext_Zbkb)) & sizeof(xlen) == 32
<-> 0b011010011000 @ rs1 @ 0b101 @ rd @ 0b0010011 if (haveZbb() | extensionEnabled(Ext_Zbkb)) & sizeof(xlen) == 32

mapping clause encdec = RISCV_REV8(rs1, rd) if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64
<-> 0b011010111000 @ rs1 @ 0b101 @ rd @ 0b0010011 if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64
mapping clause encdec = RISCV_REV8(rs1, rd) if (haveZbb() | extensionEnabled(Ext_Zbkb)) & sizeof(xlen) == 64
<-> 0b011010111000 @ rs1 @ 0b101 @ rd @ 0b0010011 if (haveZbb() | extensionEnabled(Ext_Zbkb)) & sizeof(xlen) == 64

mapping clause assembly = RISCV_REV8(rs1, rd)
<-> "rev8" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)
Expand Down
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