Updates for consistency between F, D, Q, and Zfh. Complete implementa…

…tion of fmin/fmax for Q
riscv · Apr 7, 2024 · 46fd029 · 46fd029
1 parent aa62055
commit 46fd029
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Showing 7 changed files with 188 additions and 133 deletions.
diff --git a/model/riscv_fdext_control.sail b/model/riscv_fdext_control.sail
@@ -6,14 +6,14 @@
 /*  SPDX-License-Identifier: BSD-2-Clause                                                */
 /*=======================================================================================*/
 
-/* **************************************************************** */
-/* Floating point register file and accessors for F, D extensions   */
-/* Floating point CSR and accessors                                 */
-/* **************************************************************** */
+/* ***************************************************************** */
+/* Floating point register file and accessors for F, D, Q extensions */
+/* Floating point CSR and accessors                                  */
+/* ***************************************************************** */
 
-/* Original version written by Rishiyur S. Nikhil, Sept-Oct 2019    */
+/* Original version written by Rishiyur S. Nikhil, Sept-Oct 2019     */
 
-/* **************************************************************** */
+/* ***************************************************************** */
 
 /* val clause ext_is_CSR_defined : (csreg, Privilege) -> bool */
 

diff --git a/model/riscv_fdext_regs.sail b/model/riscv_fdext_regs.sail
@@ -15,13 +15,17 @@
 
 /* **************************************************************** */
 /* NaN boxing/unboxing.                                             */
-/* When 16-bit floats (half-precision) are stored in 32/64-bit regs  */
-/* they must be 'NaN boxed'.                                         */
-/* When 16-bit floats (half-precision) are read from 32/64-bit regs  */
-/* they must be 'NaN unboxed'.                                       */
-/* When 32-bit floats (single-precision) are stored in 64-bit regs  */
+/* When 16-bit floats (half-precision) are stored in 32/64/128-bit  */
+/* regs they must be 'NaN boxed'.                                   */
+/* When 16-bit floats (half-precision) are read from 32/64/128-bit  */
+/* regs they must be 'NaN unboxed'.                                 */
+/* When 32-bit floats (single-precision) are stored in 64/128-bit   */
+/* regs they must be 'NaN boxed'.                                   */
+/* When 32-bit floats (single-precision) are read from 64/128-bit   */
+/* regs they must be 'NaN unboxed'.                                 */
+/* When 64-bit floats (double-precision) are stored in 128-bit regs */
 /* they must be 'NaN boxed' (upper 32b all ones).                   */
-/* When 32-bit floats (single-precision) are read from 64-bit regs  */
+/* When 64-bit floats (double-precision) are read from 128-bit regs */
 /* they must be 'NaN unboxed'.                                      */
 
 function canonical_NaN_H() -> bits(16) = 0x_7e00
@@ -290,9 +294,24 @@ function wF_D(i, data) = {
   F(i) = nan_box(data)
 }
 
+val rF_Q : bits(5) -> bits(128)
+function rF_Q(i) = {
+  assert(sizeof(flen) >= 128);
+  assert(sys_enable_fdext() & not(sys_enable_zfinx()));
+  F(i)
+}
+
+val wF_Q : (bits(5), bits(128)) -> unit
+function wF_Q(i, data) = {
+  assert(sizeof(flen) >= 128);
+  assert(sys_enable_fdext() & not(sys_enable_zfinx()));
+  F(i) = data
+}
+
 overload F_H = { rF_H, wF_H }
 overload F_S = { rF_S, wF_S }
 overload F_D = { rF_D, wF_D }
+overload F_Q = { rF_Q, wF_Q }
 
 val rF_or_X_H : bits(5) -> bits(16)
 function rF_or_X_H(i) = {

diff --git a/model/riscv_freg_type.sail b/model/riscv_freg_type.sail
@@ -60,25 +60,25 @@ enum f_bin_op_S = {FSGNJ_S, FSGNJN_S, FSGNJX_S, FMIN_S, FMAX_S, FEQ_S, FLT_S, FL
 
 enum f_madd_op_D = {FMADD_D, FMSUB_D, FNMSUB_D, FNMADD_D}
 
-enum f_madd_op_Q = {FMADD_Q, FMSUB_Q, FNMSUB_Q, FNMADD_Q}
-
 enum f_bin_rm_op_D = {FADD_D, FSUB_D, FMUL_D, FDIV_D}
 
-enum f_bin_rm_op_Q = {FADD_Q, FSUB_Q, FMUL_Q, FDIV_Q}
-
 enum f_un_rm_op_D = {FSQRT_D, FCVT_W_D, FCVT_WU_D, FCVT_D_W, FCVT_D_WU,    // RV32 and RV64
                      FCVT_S_D, FCVT_D_S,
                      FCVT_L_D, FCVT_LU_D, FCVT_D_L, FCVT_D_LU}             // RV64 only
 
+enum f_bin_op_D = {FSGNJ_D, FSGNJN_D, FSGNJX_D, FMIN_D, FMAX_D, FEQ_D, FLT_D, FLE_D}
+
+enum f_un_op_D = {FCLASS_D,            /* RV32 and RV64 */
+                  FMV_X_D, FMV_D_X}    /* RV64 only */
+
+enum f_madd_op_Q = {FMADD_Q, FMSUB_Q, FNMSUB_Q, FNMADD_Q}
+
+enum f_bin_rm_op_Q = {FADD_Q, FSUB_Q, FMUL_Q, FDIV_Q}
+
 enum f_un_rm_op_Q = {FSQRT_Q, FCVT_W_Q, FCVT_WU_Q, FCVT_Q_W, FCVT_Q_WU,    // RV32 and RV64
                      FCVT_S_Q, FCVT_Q_S, FCVT_D_Q, FCVT_Q_D,
                      FCVT_L_Q, FCVT_LU_Q, FCVT_Q_L, FCVT_Q_LU}             // RV64 only
 
-enum f_bin_op_D = {FSGNJ_D, FSGNJN_D, FSGNJX_D, FMIN_D, FMAX_D, FEQ_D, FLT_D, FLE_D}
-
 enum f_bin_op_Q = {FSGNJ_Q, FSGNJN_Q, FSGNJX_Q, FMIN_Q, FMAX_Q, FEQ_Q, FLT_Q, FLE_Q}
 
-enum f_un_op_D = {FCLASS_D,            /* RV32 and RV64 */
-                  FMV_X_D, FMV_D_X}    /* RV64 only */
-
 enum f_un_op_Q = {FCLASS_Q}
diff --git a/model/riscv_insts_dext.sail b/model/riscv_insts_dext.sail
@@ -16,9 +16,9 @@
 
 /* **************************************************************** */
 /* IMPORTANT!                                                       */
-/* The files 'riscv_insts_fext.sail', 'riscv_insts_dext.sail' and   */
-/* 'riscv_insts_zfh.sail' define the F, D and Zfh extensions,       */
-/* respectively.                                                    */
+/* The files 'riscv_insts_fext.sail', 'riscv_insts_dext.sail',      */
+/* 'riscv_insts_qext.sail' and 'riscv_insts_zfh.sail' define the    */
+/* F, D, Q and Zfh extensions, respectively.                        */
 /* The texts follow each other very closely; please try to maintain */
 /* this correspondence as the files are maintained for bug-fixes,   */
 /* improvements, and version updates.                               */

diff --git a/model/riscv_insts_fext.sail b/model/riscv_insts_fext.sail
@@ -16,9 +16,9 @@
 
 /* **************************************************************** */
 /* IMPORTANT!                                                       */
-/* The files 'riscv_insts_fext.sail', 'riscv_insts_dext.sail' and   */
-/* 'riscv_insts_zfh.sail' define the F, D and Zfh extensions,       */
-/* respectively.                                                    */
+/* The files 'riscv_insts_fext.sail', 'riscv_insts_dext.sail',      */
+/* 'riscv_insts_qext.sail' and 'riscv_insts_zfh.sail' define the    */
+/* F, D, Q and Zfh extensions, respectively.                        */
 /* The texts follow each other very closely; please try to maintain */
 /* this correspondence as the files are maintained for bug-fixes,   */
 /* improvements, and version updates.                               */
@@ -384,11 +384,9 @@ mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, WORD)
 mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, DOUBLE)                           if haveDExt()
                     <-> imm7 : bits(7) @ rs2 @ rs1 @ 0b011 @ imm5 : bits(5) @ 0b010_0111  if haveDExt()
 
-
 mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, QUAD)                             if haveQExt()
                     <-> imm7 : bits(7) @ rs2 @ rs1 @ 0b100 @ imm5 : bits(5) @ 0b010_0111  if haveQExt()
 
-
 /* Execution semantics ================================ */
 
 val process_fstore : (xlenbits, MemoryOpResult(bool)) -> Retired