Add support for B extension

This adds support for the B extension. If `misa[B]` is set then Zba, Zbb and Zbs are supported. There's a command line flag for this: `-B`. Note that even if you don't support B then you're allowed to support Zba, Zbb and Zbs anyway, and the Sail model currently does. In other words, currently passing `-B` only changes `misa[B]`.

In future we will allow enabling the sub extensions individually.

c_emulator/riscv_platform.c

@@ -57,6 +57,11 @@ bool sys_enable_vext(unit u)
   return rv_enable_vext;
 }
 
+bool sys_enable_bext(unit u)
+{
+  return rv_enable_bext;
+}
+
 uint64_t sys_pmp_count(unit u)
 {
   return rv_pmp_count;

c_emulator/riscv_platform.h

@@ -10,6 +10,7 @@ bool sys_enable_zfinx(unit);
 bool sys_enable_writable_misa(unit);
 bool sys_enable_writable_fiom(unit);
 bool sys_enable_vext(unit);
+bool sys_enable_bext(unit);
 
 uint64_t sys_pmp_count(unit);
 uint64_t sys_pmp_grain(unit);

c_emulator/riscv_platform_impl.c

@@ -14,6 +14,7 @@ bool rv_enable_next = false;
 bool rv_enable_writable_misa = true;
 bool rv_enable_fdext = true;
 bool rv_enable_vext = true;
+bool rv_enable_bext = false;
 
 bool rv_enable_dirty_update = false;
 bool rv_enable_misaligned = false;

c_emulator/riscv_platform_impl.h

@@ -18,6 +18,7 @@ extern bool rv_enable_rvc;
 extern bool rv_enable_next;
 extern bool rv_enable_fdext;
 extern bool rv_enable_vext;
+extern bool rv_enable_bext;
 extern bool rv_enable_writable_misa;
 extern bool rv_enable_dirty_update;
 extern bool rv_enable_misaligned;

c_emulator/riscv_sim.c

@@ -250,6 +250,7 @@ static int process_args(int argc, char **argv)
   while (true) {
     c = getopt_long(argc, argv,
                     "a"
+                    "B"
                     "d"
                     "m"
                     "P"
@@ -284,6 +285,10 @@ static int process_args(int argc, char **argv)
     case 'a':
       report_arch();
       break;
+    case 'B':
+      fprintf(stderr, "enabling B extension.\n");
+      rv_enable_bext = true;
+      break;
     case 'd':
       fprintf(stderr, "enabling dirty update.\n");
       rv_enable_dirty_update = true;

model/riscv_sys_control.sail

@@ -483,6 +483,7 @@ function init_sys() -> unit = {
   misa[MXL] = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64);
   misa[A]   = 0b1;                             /* atomics */
   misa[C]   = bool_to_bits(sys_enable_rvc());  /* RVC */
+  misa[B]   = bool_to_bits(sys_enable_bext()); /* Bit-manipulation */
   misa[I]   = 0b1;                             /* base integer ISA */
   misa[M]   = 0b1;                             /* integer multiply/divide */
   misa[U]   = 0b1;                             /* user-mode */

model/riscv_sys_regs.sail

@@ -105,6 +105,9 @@ val sys_pmp_grain = {c: "sys_pmp_grain", ocaml: "Platform.pmp_grain", _: "sys_pm
 /* whether misa.v was enabled at boot */
 val sys_enable_vext = {c: "sys_enable_vext", ocaml: "Platform.enable_vext", _: "sys_enable_vext"} : unit -> bool
 
+/* whether misa.b was enabled at boot */
+val sys_enable_bext = {c: "sys_enable_bext", ocaml: "Platform.enable_bext", _: "sys_enable_bext"} : unit -> bool
+
 /* This function allows an extension to veto a write to Misa
    if it would violate an alignment restriction on
    unsetting C. If it returns true the write will have no effect. */
@@ -136,10 +139,11 @@ function haveNExt()    -> bool = misa[N] == 0b1
 /* see below for F and D (and Z*inx counterparts) extension tests */
 
 /* BitManip extension support. */
-function haveZba()  -> bool = true
-function haveZbb()  -> bool = true
+function haveBExt() -> bool = misa[B] == 0b1
+function haveZba()  -> bool = true | haveBExt()
+function haveZbb()  -> bool = true | haveBExt()
+function haveZbs()  -> bool = true | haveBExt()
 function haveZbc()  -> bool = true
-function haveZbs()  -> bool = true
 
 /* Zfa (additional FP) extension */
 function haveZfa()  -> bool = true

ocaml_emulator/platform.ml

@@ -14,6 +14,7 @@ let config_enable_svinval              = ref false
 let config_enable_zcb                  = ref false
 let config_enable_writable_fiom        = ref true
 let config_enable_vext                 = ref true
+let config_enable_bext                 = ref false
 let config_pmp_count                   = ref Big_int.zero
 let config_pmp_grain                   = ref Big_int.zero
 
@@ -87,6 +88,7 @@ let enable_rvc ()                    = !config_enable_rvc
 let enable_next ()                   = !config_enable_next
 let enable_fdext ()                  = false
 let enable_vext ()                   = !config_enable_vext
+let enable_bext ()                   = !config_enable_bext
 let enable_dirty_update ()           = !config_enable_dirty_update
 let enable_misaligned_access ()      = !config_enable_misaligned_access
 let mtval_has_illegal_inst_bits ()   = !config_mtval_has_illegal_inst_bits

ocaml_emulator/riscv_ocaml_sim.ml

@@ -68,6 +68,9 @@ let options = Arg.align ([("-dump-dts",
                           ("-disable-vext",
                            Arg.Clear P.config_enable_vext,
                            " disable the RVV extension on boot");
+                          ("-enable-bext",
+                           Arg.Clear P.config_enable_bext,
+                           " enable the B extension on boot");
                           ("-disable-writable-misa-c",
                            Arg.Clear P.config_enable_writable_misa,
                            " leave misa hardwired to its initial value");