Replace some bits(12)s with csreg

Very minor. Uses an existing type alias.
riscv · May 14, 2024 · 52841d8 · 52841d8
1 parent e1242d8
commit 52841d8
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diff --git a/model/riscv_ext_regs.sail b/model/riscv_ext_regs.sail
@@ -28,7 +28,7 @@ function ext_rvfi_init () = {
 THIS(csrno, priv, isWrite) allows an extension to block access to csrno,
 at Privilege level priv. It should return true if the access is allowed.
 */
-val ext_check_CSR : (bits(12), Privilege, bool) -> bool
+val ext_check_CSR : (csreg, Privilege, bool) -> bool
 function ext_check_CSR (csrno, p, isWrite) = true
 
 /*!

diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
@@ -10,7 +10,7 @@
 /* This file specifies the instructions in the 'Zicsr' extension. */
 
 /* ****************************************************************** */
-union clause ast = CSR : (bits(12), regidx, regidx, bool, csrop)
+union clause ast = CSR : (csreg, regidx, regidx, bool, csrop)
 
 mapping encdec_csrop : csrop <-> bits(2) = {
  CSRRW <-> 0b01,