remove non-existent CSR sedeleg

riscv · Aug 29, 2024 · 5ed8895 · 5ed8895
1 parent 05b845c
commit 5ed8895
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Showing 4 changed files with 1 addition and 21 deletions.
diff --git a/model/riscv_csr_map.sail b/model/riscv_csr_map.sail
@@ -38,7 +38,6 @@ mapping clause csr_name_map = 0xC82  <-> "instreth"
 /* TODO: other hpm counters */
 /* supervisor trap setup */
 mapping clause csr_name_map = 0x100  <-> "sstatus"
-mapping clause csr_name_map = 0x102  <-> "sedeleg"
 mapping clause csr_name_map = 0x103  <-> "sideleg"
 mapping clause csr_name_map = 0x104  <-> "sie"
 mapping clause csr_name_map = 0x105  <-> "stvec"

diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
@@ -76,8 +76,6 @@ function readCSR csr : csreg -> xlenbits = {
 
     /* supervisor mode */
     (0x100,  _) => lower_mstatus(mstatus).bits,
-    (0x102,  _) => sedeleg.bits,
-    (0x103,  _) => sideleg.bits,
     (0x104,  _) => lower_mie(mie, mideleg).bits,
     (0x105,  _) => get_stvec(),
     (0x106,  _) => zero_extend(scounteren.bits),
@@ -157,7 +155,6 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = {
 
     /* supervisor mode */
     (0x100,  _) => { mstatus = legalize_sstatus(mstatus, value); Some(mstatus.bits) },
-    (0x102,  _) => { sedeleg = legalize_sedeleg(sedeleg, value); Some(sedeleg.bits) },
     (0x103,  _) => { sideleg.bits = value; Some(sideleg.bits) }, /* TODO: does this need legalization? */
     (0x104,  _) => { mie = legalize_sie(mie, mideleg, value); Some(mie.bits) },
     (0x105,  _) => { Some(set_stvec(value)) },

diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
@@ -63,7 +63,6 @@ function is_CSR_defined (csr : csreg) -> bool =
     /* supervisor mode: trap setup */
     0x100 => extensionEnabled(Ext_S), // sstatus
     0x102 => extensionEnabled(Ext_S) & extensionEnabled(Ext_N), // sedeleg
-    0x103 => extensionEnabled(Ext_S) & extensionEnabled(Ext_N), // sideleg
     0x104 => extensionEnabled(Ext_S), // sie
     0x105 => extensionEnabled(Ext_S), // stvec
     0x106 => extensionEnabled(Ext_S), // scounteren
@@ -171,7 +170,7 @@ function exception_delegatee(e : ExceptionType, p : Privilege) -> Privilege = {
   let super = bit_to_bool(medeleg.bits[idx]);
   /* if S-mode is absent, medeleg delegates to U-mode if 'N' is supported. */
   let user  = if   extensionEnabled(Ext_S)
-              then super & extensionEnabled(Ext_N) & bit_to_bool(sedeleg.bits[idx])
+              then super & extensionEnabled(Ext_N) 
               else super & extensionEnabled(Ext_N);
   let deleg = if      extensionEnabled(Ext_U) & user  then User
               else if extensionEnabled(Ext_S) & super then Supervisor

diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
@@ -568,22 +568,7 @@ function legalize_sstatus(m : Mstatus, v : xlenbits) -> Mstatus = {
   legalize_mstatus(m, lift_sstatus(m, Mk_Sstatus(v)).bits)
 }
 
-bitfield Sedeleg : xlenbits = {
-  UEnvCall          : 8,
-  SAMO_Access_Fault : 7,
-  SAMO_Addr_Align   : 6,
-  Load_Access_Fault : 5,
-  Load_Addr_Align   : 4,
-  Breakpoint        : 3,
-  Illegal_Instr     : 2,
-  Fetch_Access_Fault: 1,
-  Fetch_Addr_Align  : 0
-}
-register sedeleg : Sedeleg
 
-function legalize_sedeleg(s : Sedeleg, v : xlenbits) -> Sedeleg = {
-  Mk_Sedeleg(zero_extend(v[8..0]))
-}
 
 bitfield Sinterrupts : xlenbits = {
   SEI : 9,  /* external interrupts */