Replace old virtual memory code with new (details follow)

  Old code had much 'cut-and-paste' replication for RV32 (Sv32) and
  RV64 (Sv39, Sv48), and was scattered over several files.

  New code unifies them into single set of parameterized functions
  that works for RV32/RV64 and Sv32/Sv39/Sv48 (and is ready for Sv57).

  Deleted old files:
    riscv_vmem_common.sail    riscv_pte.sail          riscv_ptw.sail
    riscv_vmem_rv32.sail      riscv_vmem_rv64.sail
    riscv_vmem_sv32.sail      riscv_vmem_sv39.sail    riscv_vmem_sv48.sail

  Added 1 new file, where the main vmem code sits:
    riscv_vmem.sail

  Modified (to be compatible with new code, and to isolate TLB stuff
  into one file, since TLBs are not part of RISC-V Architecture Spec)

    riscv_vmem_tlb.sail

  Added documentation on new vmem code: doc/notes_Virtual_Memory.adoc
    Deleted older vmem files.

Makefile

@@ -68,15 +68,20 @@ SAIL_SYS_SRCS += riscv_softfloat_interface.sail riscv_fdext_regs.sail riscv_fdex
 SAIL_SYS_SRCS += riscv_csr_ext.sail         # access to CSR extensions
 SAIL_SYS_SRCS += riscv_sys_control.sail     # general exception handling
 
-SAIL_RV32_VM_SRCS = riscv_vmem_sv32.sail riscv_vmem_rv32.sail
-SAIL_RV64_VM_SRCS = riscv_vmem_sv39.sail riscv_vmem_sv48.sail riscv_vmem_rv64.sail
-
-SAIL_VM_SRCS = riscv_pte.sail riscv_ptw.sail riscv_vmem_common.sail riscv_vmem_tlb.sail
-ifeq ($(ARCH),RV32)
-SAIL_VM_SRCS += $(SAIL_RV32_VM_SRCS)
-else
-SAIL_VM_SRCS += $(SAIL_RV64_VM_SRCS)
-endif
+# Virtual Memory support: (2023-11) OLD VM CODE replaced by NEW VM CODE
+#   (see doc/notes_Virtual_Memory.adoc)
+# OLD VM CODE
+#   SAIL_RV32_VM_SRCS = riscv_vmem_sv32.sail riscv_vmem_rv32.sail
+#   SAIL_RV64_VM_SRCS = riscv_vmem_sv39.sail riscv_vmem_sv48.sail riscv_vmem_rv64.sail
+#   SAIL_VM_SRCS = riscv_pte.sail riscv_ptw.sail riscv_vmem_common.sail riscv_vmem_tlb.sail
+#   ifeq ($(ARCH),RV32)
+#   SAIL_VM_SRCS += $(SAIL_RV32_VM_SRCS)
+#   else
+#   SAIL_VM_SRCS += $(SAIL_RV64_VM_SRCS)
+#   endif
+# NEW VM CODE
+SAIL_VM_SRCS += riscv_vmem_tlb.sail
+SAIL_VM_SRCS += riscv_vmem.sail
 
 # Non-instruction sources
 PRELUDE = prelude.sail prelude_mapping.sail $(SAIL_XLEN) $(SAIL_FLEN) $(SAIL_VLEN) prelude_mem_metadata.sail prelude_mem.sail