add blanks

riscv · Nov 26, 2023 · bbac057 · bbac057
1 parent e0a029b
commit bbac057
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
@@ -634,6 +634,7 @@ bitfield Sstatus : xlenbits = {
   SIE  : 1,
   UIE  : 0
 }
+
 /* sstatus is a view of mstatus, so there is no register defined. */
 function get_sstatus_UXL(s : Sstatus) -> arch_xlen = {
   let m = Mk_Mstatus(s.bits());
@@ -645,6 +646,7 @@ function set_sstatus_UXL(s : Sstatus, a : arch_xlen) -> Sstatus = {
   let m = set_mstatus_UXL(m, a);
   Mk_Sstatus(m.bits())
 }
+
 function lower_mstatus(m : Mstatus) -> Sstatus = {
   let s = Mk_Sstatus(zero_extend(0b0));
   let s = update_SD(s, m.SD());