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remove N extension
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@KotorinMinami
KotorinMinami committed Sep 6, 2024
1 parent 05b845c commit bccd5ef
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Showing 9 changed files with 15 additions and 256 deletions.
4 changes: 1 addition & 3 deletions Makefile
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Expand Up @@ -23,7 +23,7 @@ SAIL_VLEN := riscv_vlen.sail

# Instruction sources, depending on target
SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail
SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_zca.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail
SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_zca.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_hints.sail
SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_zcf.sail
SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_zcd.sail

Expand Down Expand Up @@ -70,10 +70,8 @@ SAIL_RMEM_INST_SRCS = riscv_insts_begin.sail $(SAIL_RMEM_INST) riscv_insts_end.s
# System and platform sources
SAIL_SYS_SRCS = riscv_csr_map.sail
SAIL_SYS_SRCS += riscv_vext_control.sail # helpers for the 'V' extension
SAIL_SYS_SRCS += riscv_next_regs.sail
SAIL_SYS_SRCS += riscv_sys_exceptions.sail # default basic helpers for exception handling
SAIL_SYS_SRCS += riscv_sync_exception.sail # define the exception structure used in the model
SAIL_SYS_SRCS += riscv_next_control.sail # helpers for the 'N' extension
SAIL_SYS_SRCS += riscv_softfloat_interface.sail riscv_fdext_regs.sail riscv_fdext_control.sail
SAIL_SYS_SRCS += riscv_csr_ext.sail # access to CSR extensions
SAIL_SYS_SRCS += riscv_sys_control.sail # general exception handling
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13 changes: 1 addition & 12 deletions model/riscv_csr_map.sail
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Expand Up @@ -12,16 +12,7 @@ val csr_name_map : csreg <-> string

scattered mapping csr_name_map

/* user trap setup */
mapping clause csr_name_map = 0x000 <-> "ustatus"
mapping clause csr_name_map = 0x004 <-> "uie"
mapping clause csr_name_map = 0x005 <-> "utvec"
/* user trap handling */
mapping clause csr_name_map = 0x040 <-> "uscratch"
mapping clause csr_name_map = 0x041 <-> "uepc"
mapping clause csr_name_map = 0x042 <-> "ucause"
mapping clause csr_name_map = 0x043 <-> "utval"
mapping clause csr_name_map = 0x044 <-> "uip"

/* user floating-point context */
mapping clause csr_name_map = 0x001 <-> "fflags"
mapping clause csr_name_map = 0x002 <-> "frm"
Expand All @@ -38,8 +29,6 @@ mapping clause csr_name_map = 0xC82 <-> "instreth"
/* TODO: other hpm counters */
/* supervisor trap setup */
mapping clause csr_name_map = 0x100 <-> "sstatus"
mapping clause csr_name_map = 0x102 <-> "sedeleg"
mapping clause csr_name_map = 0x103 <-> "sideleg"
mapping clause csr_name_map = 0x104 <-> "sie"
mapping clause csr_name_map = 0x105 <-> "stvec"
mapping clause csr_name_map = 0x106 <-> "scounteren"
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26 changes: 0 additions & 26 deletions model/riscv_insts_next.sail
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4 changes: 0 additions & 4 deletions model/riscv_insts_zicsr.sail
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Expand Up @@ -76,8 +76,6 @@ function readCSR csr : csreg -> xlenbits = {

/* supervisor mode */
(0x100, _) => lower_mstatus(mstatus).bits,
(0x102, _) => sedeleg.bits,
(0x103, _) => sideleg.bits,
(0x104, _) => lower_mie(mie, mideleg).bits,
(0x105, _) => get_stvec(),
(0x106, _) => zero_extend(scounteren.bits),
Expand Down Expand Up @@ -157,8 +155,6 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = {

/* supervisor mode */
(0x100, _) => { mstatus = legalize_sstatus(mstatus, value); Some(mstatus.bits) },
(0x102, _) => { sedeleg = legalize_sedeleg(sedeleg, value); Some(sedeleg.bits) },
(0x103, _) => { sideleg.bits = value; Some(sideleg.bits) }, /* TODO: does this need legalization? */
(0x104, _) => { mie = legalize_sie(mie, mideleg, value); Some(mie.bits) },
(0x105, _) => { Some(set_stvec(value)) },
(0x106, _) => { scounteren = legalize_scounteren(scounteren, value); Some(zero_extend(scounteren.bits)) },
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40 changes: 0 additions & 40 deletions model/riscv_next_control.sail
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91 changes: 0 additions & 91 deletions model/riscv_next_regs.sail
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31 changes: 6 additions & 25 deletions model/riscv_sys_control.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,8 @@ function is_CSR_defined (csr : csreg) -> bool =
/* machine mode: trap setup */
0x300 => true, // mstatus
0x301 => true, // misa
0x302 => extensionEnabled(Ext_S) | extensionEnabled(Ext_N), // medeleg
0x303 => extensionEnabled(Ext_S) | extensionEnabled(Ext_N), // mideleg
0x302 => extensionEnabled(Ext_S) , // medeleg
0x303 => extensionEnabled(Ext_S) , // mideleg
0x304 => true, // mie
0x305 => true, // mtvec
0x306 => extensionEnabled(Ext_U), // mcounteren
Expand Down Expand Up @@ -62,8 +62,6 @@ function is_CSR_defined (csr : csreg) -> bool =

/* supervisor mode: trap setup */
0x100 => extensionEnabled(Ext_S), // sstatus
0x102 => extensionEnabled(Ext_S) & extensionEnabled(Ext_N), // sedeleg
0x103 => extensionEnabled(Ext_S) & extensionEnabled(Ext_N), // sideleg
0x104 => extensionEnabled(Ext_S), // sie
0x105 => extensionEnabled(Ext_S), // stvec
0x106 => extensionEnabled(Ext_S), // scounteren
Expand Down Expand Up @@ -169,12 +167,7 @@ val cancel_reservation = {ocaml: "Platform.cancel_reservation", interpreter: "Pl
function exception_delegatee(e : ExceptionType, p : Privilege) -> Privilege = {
let idx = num_of_ExceptionType(e);
let super = bit_to_bool(medeleg.bits[idx]);
/* if S-mode is absent, medeleg delegates to U-mode if 'N' is supported. */
let user = if extensionEnabled(Ext_S)
then super & extensionEnabled(Ext_N) & bit_to_bool(sedeleg.bits[idx])
else super & extensionEnabled(Ext_N);
let deleg = if extensionEnabled(Ext_U) & user then User
else if extensionEnabled(Ext_S) & super then Supervisor
let deleg = if extensionEnabled(Ext_S) & super then Supervisor
else Machine;
/* We cannot transition to a less-privileged mode. */
if privLevel_to_bits(deleg) <_u privLevel_to_bits(p)
Expand Down Expand Up @@ -240,24 +233,12 @@ function getPendingSet(priv : Privilege) -> option((xlenbits, Privilege)) = {
*/
let mIE = priv != Machine | (priv == Machine & mstatus[MIE] == 0b1);
let sIE = extensionEnabled(Ext_S) & (priv == User | (priv == Supervisor & mstatus[SIE] == 0b1));
let uIE = extensionEnabled(Ext_N) & (priv == User & mstatus[UIE] == 0b1);
match processPending(mip, mie, mideleg.bits, mIE) {
Ints_Empty() => None(),
Ints_Pending(p) => let r = (p, Machine) in Some(r),
Ints_Delegated(d) =>
if not(extensionEnabled(Ext_S)) then {
if uIE then let r = (d, User) in Some(r)
else None()
} else {
/* the delegated bits are pending for S-mode */
match processPending(Mk_Minterrupts(d), mie, sideleg.bits, sIE) {
Ints_Empty() => None(),
Ints_Pending(p) => let r = (p, Supervisor) in Some(r),
Ints_Delegated(d) => if uIE
then let r = (d, User) in Some(r)
else None()
}
}
if not(extensionEnabled(Ext_S)) then None()
else let r = (d, Supervisor) in Some(r)
}
}
}
Expand All @@ -269,7 +250,7 @@ function dispatchInterrupt(priv : Privilege) -> option((InterruptType, Privilege
/* If we don't have different privilege levels, we don't need to check delegation.
* Absence of U-mode implies absence of S-mode.
*/
if not(extensionEnabled(Ext_U)) | (not(extensionEnabled(Ext_S)) & not(extensionEnabled(Ext_N))) then {
if not(extensionEnabled(Ext_U)) | (not(extensionEnabled(Ext_S))) then {
assert(priv == Machine, "invalid current privilege");
let enabled_pending = mip.bits & mie.bits;
match findPendingInterrupt(enabled_pending) {
Expand Down
11 changes: 1 addition & 10 deletions model/riscv_sys_exceptions.sail
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Expand Up @@ -21,8 +21,7 @@ function handle_trap_extension(p : Privilege, pc : xlenbits, u : option(unit)) -
function prepare_trap_vector(p : Privilege, cause : Mcause) -> xlenbits = {
let tvec : Mtvec = match p {
Machine => mtvec,
Supervisor => stvec,
User => utvec
Supervisor => stvec
};
match tvec_addr(tvec, cause) {
Some(epc) => epc,
Expand Down Expand Up @@ -68,9 +67,6 @@ function get_mtvec() -> xlenbits =
function get_stvec() -> xlenbits =
stvec.bits

function get_utvec() -> xlenbits =
utvec.bits

function set_mtvec(value : xlenbits) -> xlenbits = {
mtvec = legalize_tvec(mtvec, value);
mtvec.bits
Expand All @@ -80,8 +76,3 @@ function set_stvec(value : xlenbits) -> xlenbits = {
stvec = legalize_tvec(stvec, value);
stvec.bits
}

function set_utvec(value : xlenbits) -> xlenbits = {
utvec = legalize_tvec(utvec, value);
utvec.bits
}
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