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Add zvbc extension
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@Yui5427
Yui5427 committed Sep 16, 2024
1 parent f6ca840 commit c79262f
Showing 1 changed file with 24 additions and 7 deletions.
31 changes: 24 additions & 7 deletions model/riscv_insts_zvbc.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -9,11 +9,19 @@
enum clause extension = Ext_Zvbc
function clause extensionEnabled(Ext_Zvbc) = true

mapping vm_name : bits(1) <-> string = {
0b0 <-> "0",
0b1 <-> "1"
}

union clause ast = VCLMUL_VV : (bits(1), regidx, regidx, regidx)

mapping clause encdec = VCLMUL_VV (vm, vs2, vs1, vd) if extensionEnabled(Ext_Zvbc)
<-> 0b001100 @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if extensionEnabled(Ext_Zvbc)

mapping clause assembly = VCLMUL_VV (vm, vs2, vs1, vd)
<-> "vclmul.vv" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ sep() ^ vm_name(vm)

function clause execute (VCLMUL_VV(vm, vs2, vs1, vd)) = {
let SEW = get_sew();
let LMUL_pow = get_lmul_pow();
Expand All @@ -26,7 +34,7 @@ function clause execute (VCLMUL_VV(vm, vs2, vs1, vd)) = {

var result : vector('n, dec, bits('m)) = undefined;
var mask : vector('n, dec, bool) = undefined;
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);
let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);

let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);
Expand All @@ -50,6 +58,9 @@ union clause ast = VCLMUL_VX : (bits(1), regidx, regidx, regidx)
mapping clause encdec = VCLMUL_VX (vm, vs2, rs1, vd) if extensionEnabled(Ext_Zvbc)
<-> 0b001100 @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if extensionEnabled(Ext_Zvbc)

mapping clause assembly = VCLMUL_VX (vm, vs2, rs1, vd)
<-> "vclmul.vx" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ sep() ^ vm_name(vm)

function clause execute (VCLMUL_VX(vm, vs2, rs1, vd)) = {
let SEW = get_sew();
let LMUL_pow = get_lmul_pow();
Expand All @@ -60,7 +71,7 @@ function clause execute (VCLMUL_VX(vm, vs2, rs1, vd)) = {

var result : vector('n, dec, bits('m)) = undefined;
var mask : vector('n, dec, bool) = undefined;
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);
let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);

let rs1_val : bits('m) = get_scalar(rs1, SEW);
Expand All @@ -84,6 +95,9 @@ union clause ast = VCLMULH_VV : (bits(1), regidx, regidx, regidx)
mapping clause encdec = VCLMULH_VV (vm, vs2, vs1, vd) if extensionEnabled(Ext_Zvbc)
<-> 0b001101 @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if extensionEnabled(Ext_Zvbc)

mapping clause assembly = VCLMULH_VV (vm, vs2, vs1, vd)
<-> "vclmulh.vv" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ sep() ^ vm_name(vm)

function clause execute (VCLMULH_VV(vm, vs2, vs1, vd)) = {
let SEW = get_sew();
let LMUL_pow = get_lmul_pow();
Expand All @@ -96,7 +110,7 @@ function clause execute (VCLMULH_VV(vm, vs2, vs1, vd)) = {

var result : vector('n, dec, bits('m)) = undefined;
var mask : vector('n, dec, bool) = undefined;
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);
let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);

let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);
Expand All @@ -107,7 +121,7 @@ function clause execute (VCLMULH_VV(vm, vs2, vs1, vd)) = {
foreach (i from 0 to (num_elem - 1)) {
if mask[i] then {
foreach (n from 0 to (SEW - 1))
if vs2_val[i][n] == bitone then result[i] = result[i] ^ (vs1_val[i] >> n);
if vs2_val[i][n] == bitone then result[i] = result[i] ^ (vs1_val[i] >> (SEW - n));
write_vreg(num_elem, SEW, LMUL_pow, vd, result);
};
};
Expand All @@ -118,7 +132,10 @@ function clause execute (VCLMULH_VV(vm, vs2, vs1, vd)) = {
union clause ast = VCLMULH_VX : (bits(1), regidx, regidx, regidx)

mapping clause encdec = VCLMULH_VX (vm, vs2, rs1, vd) if extensionEnabled(Ext_Zvbc)
<-> 0b001101 @ vm @ vs2 @ rs1 @ 0b111 @ vd @ 0b1010111 if extensionEnabled(Ext_Zvbc)
<-> 0b001101 @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if extensionEnabled(Ext_Zvbc)

mapping clause assembly = VCLMULH_VX (vm, vs2, rs1, vd)
<-> "vclmulh.vx" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ sep() ^ vm_name(vm)

function clause execute (VCLMULH_VX(vm, vs2, rs1, vd)) = {
let SEW = get_sew();
Expand All @@ -130,7 +147,7 @@ function clause execute (VCLMULH_VX(vm, vs2, rs1, vd)) = {

var result : vector('n, dec, bits('m)) = undefined;
var mask : vector('n, dec, bool) = undefined;
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);
let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);

let rs1_val : bits('m) = get_scalar(rs1, SEW);
Expand All @@ -141,7 +158,7 @@ function clause execute (VCLMULH_VX(vm, vs2, rs1, vd)) = {
foreach (i from 0 to (num_elem - 1)) {
if mask[i] then {
foreach (n from 0 to (SEW - 1))
if vs2_val[i][n] == bitone then result[i] = result[i] ^ (rs1_val >> n);
if vs2_val[i][n] == bitone then result[i] = result[i] ^ (rs1_val >> (SEW - n));
write_vreg(num_elem, SEW, LMUL_pow, vd, result);
};
};
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