add amocas specific addr check

riscv · Aug 18, 2023 · d0cc13c · d0cc13c
1 parent 8949f86
commit d0cc13c
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Showing 2 changed files with 8 additions and 2 deletions.
diff --git a/model/riscv_addr_checks.sail b/model/riscv_addr_checks.sail
@@ -121,6 +121,13 @@ function ext_data_get_addr(base : regidx, offset : xlenbits, acc : AccessType(ex
  let addr = X(base) + offset in
  Ext_DataAddr_OK(addr)
 
+/* Default AMO data addr is just base register.
+ Extensions might override and add additional checks. */
+function ext_data_get_amo_addr(base : regidx, acc : AccessType(ext_access_type), width : amo_word_width)
+ -> Ext_DataAddr_Check(ext_data_addr_error) =
+ let addr = X(base) in
+ Ext_DataAddr_OK(addr)
+
 function ext_handle_data_check_error(err : ext_data_addr_error) -> unit =
  ()
 

diff --git a/model/riscv_insts_aext.sail b/model/riscv_insts_aext.sail
@@ -298,9 +298,8 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
  if haveAtomics() then {
  /* Get the address, X(rs1) (no offset).
  * Some extensions perform additional checks on address validity.
- * For obtaining virtual address, the width is not needed.
  */
- match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), BYTE) {
+ match ext_data_get_amo_addr(rs1, ReadWrite(Data, Data), width) {
  Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
  Ext_DataAddr_OK(vaddr) => {
  match translateAddr(vaddr, ReadWrite(Data, Data)) {