Updated the Zjpm

riscv · Sep 16, 2024 · e36958b · e36958b
1 parent 07bd33b
commit e36958b
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
@@ -58,8 +58,8 @@ function is_CSR_defined (csr : csreg) -> bool =
     0xB82 => sizeof(xlen) == 32, // minstreth
 
     /* machine protection */
-    0x747 => p == Machine, // mseccfg
-    0x757 => p == Machine & (sizeof(xlen) == 32), // mseccfgh      
+    0x747 => true, // mseccfg
+    0x757 => sizeof(xlen) == 32, // mseccfgh      
 
     /* disabled trigger/debug module */
     0x7a0 => true,