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Sail support for rvv #149
Sail support for rvv #149
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,24 @@ | ||
name: CI | ||
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on: [push, pull_request] | ||
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jobs: | ||
build: | ||
runs-on: [ubuntu-18.04] | ||
steps: | ||
- name: Install opam2 | ||
run: | | ||
sudo add-apt-repository -y ppa:avsm/ppa | ||
sudo apt install -y opam zlib1g-dev pkg-config libgmp-dev z3 | ||
- name: Init opam | ||
run: opam init --disable-sandboxing -y | ||
- name: Install sail | ||
run: opam install -y sail | ||
- name: Check out repository code | ||
uses: actions/checkout@HEAD | ||
with: | ||
submodules: true | ||
- name: Build RV32 simulators | ||
run: eval $(opam env) && make ARCH=RV32 -j2 csim rvfi | ||
- name: Build RV64 simulators | ||
run: eval $(opam env) && make ARCH=RV64 -j2 csim rvfi | ||
Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,24 @@ | ||
name: CI | ||
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on: [push, pull_request] | ||
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jobs: | ||
build: | ||
runs-on: [ubuntu-18.04] | ||
steps: | ||
- name: Install opam2 | ||
run: | | ||
sudo add-apt-repository -y ppa:avsm/ppa | ||
sudo apt install -y opam zlib1g-dev pkg-config libgmp-dev z3 | ||
- name: Init opam | ||
run: opam init --disable-sandboxing -y | ||
- name: Install sail | ||
run: opam install -y sail | ||
- name: Check out repository code | ||
uses: actions/checkout@HEAD | ||
with: | ||
submodules: true | ||
- name: Build RV32 simulators | ||
run: eval $(opam env) && make ARCH=RV32 -j2 csim rvfi osim | ||
- name: Build RV64 simulators | ||
run: eval $(opam env) && make ARCH=RV64 -j2 csim rvfi osim | ||
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Same as above |
Original file line number | Diff line number | Diff line change |
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@@ -16,6 +16,7 @@ else | |
endif | ||
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SAIL_FLEN := riscv_flen_D.sail | ||
SAIL_VLEN = riscv_vlen.sail | ||
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# Instruction sources, depending on target | ||
SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail | ||
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@@ -36,6 +37,8 @@ SAIL_DEFAULT_INST += riscv_insts_zks.sail | |
SAIL_DEFAULT_INST += riscv_insts_zbkb.sail | ||
SAIL_DEFAULT_INST += riscv_insts_zbkx.sail | ||
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SAIL_DEFAULT_INST += riscv_insts_vext_total.sail | ||
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SAIL_SEQ_INST = $(SAIL_DEFAULT_INST) riscv_jalr_seq.sail | ||
SAIL_RMEM_INST = $(SAIL_DEFAULT_INST) riscv_jalr_rmem.sail riscv_insts_rmem.sail | ||
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@@ -44,6 +47,7 @@ SAIL_RMEM_INST_SRCS = riscv_insts_begin.sail $(SAIL_RMEM_INST) riscv_insts_end.s | |
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# System and platform sources | ||
SAIL_SYS_SRCS = riscv_csr_map.sail | ||
SAIL_SYS_SRCS += riscv_vext_control.sail | ||
SAIL_SYS_SRCS += riscv_next_regs.sail | ||
SAIL_SYS_SRCS += riscv_sys_exceptions.sail # default basic helpers for exception handling | ||
SAIL_SYS_SRCS += riscv_sync_exception.sail # define the exception structure used in the model | ||
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@@ -63,18 +67,21 @@ SAIL_VM_SRCS += $(SAIL_RV64_VM_SRCS) | |
endif | ||
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# Non-instruction sources | ||
PRELUDE = prelude.sail prelude_mapping.sail $(SAIL_XLEN) $(SAIL_FLEN) prelude_mem_metadata.sail prelude_mem.sail | ||
PRELUDE = prelude.sail prelude_mapping.sail $(SAIL_XLEN) $(SAIL_FLEN) $(SAIL_VLEN) prelude_mem_metadata.sail prelude_mem.sail | ||
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SAIL_REGS_SRCS = riscv_reg_type.sail riscv_freg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail | ||
SAIL_REGS_SRCS += riscv_reg_type_vector.sail riscv_regs_vector.sail | ||
SAIL_REGS_SRCS += riscv_pmp_regs.sail riscv_pmp_control.sail | ||
SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS) | ||
SAIL_REGS_SRCS += riscv_types_vector.sail | ||
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SAIL_ARCH_SRCS = $(PRELUDE) | ||
SAIL_ARCH_SRCS += riscv_types_common.sail riscv_types_ext.sail riscv_types.sail | ||
SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail | ||
SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS) | ||
SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail | ||
SAIL_ARCH_SRCS += riscv_types_kext.sail # Shared/common code for the cryptography extension. | ||
#SAIL_ARCH_SRCS += riscv_types_vector.sail | ||
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SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail | ||
RVFI_STEP_SRCS = riscv_step_common.sail riscv_step_rvfi.sail riscv_decode_ext.sail riscv_fetch_rvfi.sail riscv_step.sail | ||
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@@ -197,7 +204,14 @@ riscv.smt_model: $(SAIL_SRCS) | |
cgen: $(SAIL_SRCS) model/main.sail | ||
$(SAIL) -cgen $(SAIL_FLAGS) $(SAIL_SRCS) model/main.sail | ||
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generated_definitions/ocaml/$(ARCH)/riscv.ml: $(SAIL_SRCS) Makefile | ||
riscv_vlen: FORCE | ||
ifdef VLEN | ||
ifdef ELEN | ||
python gen_vlen.py $(VLEN) $(ELEN) | ||
endif | ||
endif | ||
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generated_definitions/ocaml/$(ARCH)/riscv.ml: riscv_vlen $(SAIL_SRCS) Makefile | ||
mkdir -p generated_definitions/ocaml/$(ARCH) | ||
$(SAIL) $(SAIL_FLAGS) -ocaml -ocaml-nobuild -ocaml_build_dir generated_definitions/ocaml/$(ARCH) -o riscv $(SAIL_SRCS) | ||
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@@ -235,7 +249,7 @@ generated_definitions/ocaml/riscv_duopod_ocaml: $(PRELUDE_SRCS) model/riscv_duop | |
ocaml_emulator/tracecmp: ocaml_emulator/tracecmp.ml | ||
ocamlfind ocamlopt -annot -linkpkg -package unix $^ -o $@ | ||
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generated_definitions/c/riscv_model_$(ARCH).c: $(SAIL_SRCS) model/main.sail Makefile | ||
generated_definitions/c/riscv_model_$(ARCH).c: riscv_vlen $(SAIL_SRCS) model/main.sail Makefile | ||
mkdir -p generated_definitions/c | ||
$(SAIL) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_SRCS) model/main.sail -o $(basename $@) | ||
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@@ -248,7 +262,7 @@ $(SOFTFLOAT_LIBS): | |
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# convenience target | ||
.PHONY: csim | ||
csim: c_emulator/riscv_sim_$(ARCH) | ||
csim: c_emulator/riscv_sim_$(ARCH) | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Trim trailing space across all source files ! |
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.PHONY: osim | ||
osim: ocaml_emulator/riscv_ocaml_sim_$(ARCH) | ||
.PHONY: rvfi | ||
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@@ -10,9 +10,9 @@ function test_build () { | |
fi | ||
} | ||
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test_build make ARCH=RV32 ocaml_emulator/riscv_ocaml_sim_RV32 | ||
test_build make ARCH=RV64 ocaml_emulator/riscv_ocaml_sim_RV64 | ||
test_build make ARCH=RV32 ocaml_emulator/riscv_ocaml_sim_RV32 -j24 | ||
test_build make ARCH=RV64 ocaml_emulator/riscv_ocaml_sim_RV64 -j24 | ||
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test_build make ARCH=RV32 c_emulator/riscv_sim_RV32 | ||
test_build make ARCH=RV64 c_emulator/riscv_sim_RV64 | ||
test_build make ARCH=RV32 c_emulator/riscv_sim_RV32 -j24 | ||
test_build make ARCH=RV64 c_emulator/riscv_sim_RV64 -j24 | ||
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Comment on lines
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I dont see any reason that this is changed to exactly 24 jobs, one could argue that maybe should -j$(nproc), but I advise just to leave it as is here (in this PR) ! |
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I dont think changing workflow script does any good in this instance, if there is an issue with the CI script, that should be addressed elsewhere (issues, seperate PR), I advise you to delete this and keep the original one.