…iscv#191)

* V extension general framework and configuration setting instructions

* Update model/riscv_insts_vext_utils.sail

fix a typo

Co-authored-by: Nicolas Brunie <nibrunie@gmail.com>
Signed-off-by: BrighterW <xinlai.w@rioslab.org>

* Update model/riscv_insts_vext_vset.sail

* Revisions after Nov 22 meeting

* Update effect matching for functions in riscv_vlen.sail

* Fix code formatting issues

* Update model/riscv_insts_vext_utils.sail

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Signed-off-by: Xinlai Wan <xinlai.w@rioslab.org>

* Fix coding style issues

* Update vset instructions

Signed-off-by: BrighterW <xinlai.w@rioslab.org>
Signed-off-by: Xinlai Wan <xinlai.w@rioslab.org>
Co-authored-by: Nicolas Brunie <nibrunie@gmail.com>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>

* Add vector load / store instructions

* Modify the implementation of SEW, LMUL, VLEN and avoid real numbers in the code

* Update vstart setting in vector load / store instructions

* Remove unnecessary assert statements in vector instructions

* Fix bugs in vleff instructions and revise coding styles

* Add guards for vector encdec clauses, Avoid redundant memory access after vector load/store failure

* Add vector arithmetic & mask instructions

* Update vector EEW and EMUL checking function

* Add vector instruction illegal check functions

* Adjust code formatting for vector instruction illegal check functions

Merge approved by team at tech-golden-model meeting on 2023-03-14.

* Add vector floating-point instructions

* Update vector floating-point conversion instructions

* Update copyright headers for vector extension code

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Co-authored-by: xwan <xinlai.wan@rivai.ai>

* Add vector mask and reduction instructions

* Fix register overlap check in vector mask instructions

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Co-authored-by: xwan <xinlai.wan@rivai.ai>

To support the implementation of Zvkned extension in SAIL, this
creates the necessary infrastructure(i.e., a file to hold it, and the
extension macro), preparing the tree for the Zvkned implementation.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

All of the instructions that were introduced in the Zvk*
extensions, use a common logic that can be implemented in
functions in order to reuse them when needed and avoid
duplicate code.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

The "vaesef.vv|vs" instruction performs the final-round
encryption of the AES block cipher.

The "SubBytes" and "ShiftRows" steps are applied to each round state
element group from "vd". This is then XORed with the corresponding round
key element group in "vs2"(vector-vector form) or the scalar element group
in "vs2"(vector-scalar form).

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

The "vaesem.vv|vs" instruction performs the middle-round
encryption of the AES block cipher.

The "SubBytes", "ShiftRows" and "MixColumns" steps are applied to each
round state element group from "vd". This is then XORed with the
corresponding round key element group in "vs2"(vector-vector form) or
the scalar element group in "vs2"(vector-scalar form).

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

The "vaesdf.vv|vs" instruction performs a final-round
decryption of the AES block cipher.

The "InvShiftRows" and "InvSubBytes" steps are applied to each round state
element group from "vd". This is then XORed with the corresponding round
key element group in "vs2"(vector-vector form) or the scalar element group
in "vs2"(vector-scalar form).

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

The "vaesdm.vv|vs" instruction performs the middle-round
decryption of the AES block cipher.

The "InvShiftRows" and "InvSubBytes" steps are applied to each round state
element group from "vd". This is then XORed with the corresponding round
key element group in "vs2"(vector-vector form) or the scalar element group
in "vs2"(vector-scalar form).

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

The "vaeskf1.vi" instruction performs a single round
of the forward AES-128 KeySchedule generation.

The next round key is generated word by word from the current round
key element group in "vs2" and the immediately previous word of the
round key. The least significant word is generated using the most
significant word of the current round key as well as a round constant
which is selected by the round number.

The round number(ranges 1-10), comes from imm[3:0]; imm[4] is ignored.
We project out-of-range immediates onto in-range values by inverting
imm[3].

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

The "vaeskf2.vi" instruction performs a single round
of the forward AES-256 KeySchedule generation.

The next round key is generated word by word from the previous round
key element group in "vd" and the immediately previous word of the round
key. The least significant word of the next round key is generated by
applying a function to the most significant word of the current round
key and then XORing the result with the round constant. The round
number is used to select the round constant as well as the function.

The round number(ranges 2-14), comes from imm[3:0]; imm[4] is ignored.
We project out-of-range immediates into in-range values by inverting
imm[3].

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

The "vaesz.vs" instruction performs a round zero
encryption/decryption

This instruction is only available in ".vs" form.
The new round state output of each element group is produced
by XORing the round key "vs2" with each element group of "vd".

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

…decode_rcon

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>