Commits on Oct 30, 2023

1. Make consistent operand names …

   There are a few places where operand/field names are not consistent
   across scattered definitions for an instruction.
   
   Here, parameter `rs2` is used for encode/decode and execute, but
   `rd` is used for the same purpose in the assembly clause:
   ```
   mapping clause encdec_compressed = C_SWSP(ui76 @ ui52, rs2)
     <-> 0b110 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regidx @ 0b10
   
   function clause execute (C_SWSP(uimm, rs2)) = {
     let imm : bits(12) = zero_extend(uimm @ 0b00);
     execute(STORE(imm, rs2, sp, WORD, false, false))
   }
   
   mapping clause assembly = C_SWSP(uimm, rd)
     <-> "c.swsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(uimm)
   ```
   
   Fix these by using the operand names found in
   "The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA",
   document version 20191213, and "RISC-V Cryptography Extensions
   Volumn I: Scalar & Entropy Source Instructions", version v1.0.1.

   

   ThinkOpenly committed Oct 30, 2023
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