Commits on Nov 14, 2023

1. Fix Store-Conditional assembly operand order and add parens …

   The operand order for Store-Conditional assembly has the second
   and third operands reversed.
   
   The RISC-V Instruction Set Manual states:
   > ```
   > SC.W conditionally writes a word in rs2 to the address in rs1 [...]
   > If the SC.W succeeds, the instruction writes the word in rs2 to memory,
   > and it writes zero to rd. If the SC.W fails, the instruction does not
   > write to memory, and it writes a nonzero value to rd.
   > ```
   
   `rd` is for the return code, `rs2` is the value, and `rs1` is the memory
   address.
   
   For the syntax `sc.w A,B,(C)`:
   - `A` is where the result is stored, per convention. So, this is `rd`.
   - `B` is the value to be stored. So, this is `rs2`.
   - `C` is the address at which to store the value. So, this is `rs1`.
   
   The resulting syntax would be `stc.w rd,rs2,(rs1)`.
   
   The current assembly representation is:
   ```
   "sc." ^ size_mnemonic(size) [...] reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
   ```
   
   Note that the order is wrong. In addition, parentheses are missing around `rs2`.
   
   Fix this instance, as well as two other instances where parentheses are missing.
   
   Fixes riscv#338.
   Fixes riscv#344.
   
   Suggested-by: Tim Hutt <timothy.hutt@codasip.com>

   

   ThinkOpenly committed Nov 14, 2023
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