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This breaks extensions (e.g. CHERI) that do assign meaning to these bits and exist as users of the Sail model
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If the base priv spec says we need to raise a page fault when these bits are non-zero, I'm not sure we can ignore it. Maybe we need to add some kind of mechanism so CHERI can override the behaviour of isInvalidPTE and similar functions with its own implementations?
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The privileged specification reserves these bits for future standard use. There are two extensions - Svpbmt and Svnapot - that use some of the bits that are not present in our golden reference model. The use of bits by extensions needs to be enabled by the governing
xenvcfg
register. Not having these checks makes it a problem to use it as a golden reference as these mismatches need to be waived. I hope to provide the models for the other missing pieces in the virtual memory system architecture - Svnapot, Svpbmt, and Sv57 - and this bug fix is needed to build those. When CHERI becomes a standard extension I think it would follow the architecture and add the environment controls to enable the use of a subset of those bits that get allocated for CHERI use.There was a problem hiding this comment.
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I sent PR #393 with the Svnapot and Svpbmt extensions. Sorry, i had to duplicate contents of this PR in #393. Was trying to make updates incrementally but since this did not get merged, had to do the duplication. Please let me know if I should just close this PR since #393 is the superset.