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Replace old virtual memory code with new (details follow) #408
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RV64 (Sv39, Sv48), and was scattered over several files. New code unifies them into single set of parameterized functions that works for RV32/RV64 and Sv32/Sv39/Sv48 (and is ready for Sv57). Deleted old files: riscv_vmem_rv32.sail riscv_vmem_rv64.sail riscv_vmem_sv32.sail riscv_vmem_sv39.sail riscv_vmem_sv48.sail riscv_pte.sail riscv_ptw.sail Current files: all named riscv_vmem_* riscv_vmem.sail (root file for vmem) riscv_vmem_common.sail riscv_vmem_pte.sail riscv_vmem_ptw.sail riscv_vmem_tlb.sail riscv_vmem_types.sail Modified top-level Makefile accordingly. Added documentation on new vmem code: doc/notes_Virtual_Memory.adoc
Hi, I finally managed to do some testing of this. Didn't quite do as much as I wanted but I ran it through our CI system and it passed all the tests (about 100 tests from various sources; not all VM focused but lots of them do randomly test it). Can you just rebase & squash the commits and make the commit message subject into the normal verb tense:
Easy way to do this if you aren't a git pro:
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Thanks very much!
I’m not a git pro; I tried the commands you suggested, and spent several hours trying several variants, without success. The current (top of) the git graph in https://github.com/rsnikhil/sail-riscv is:
I assume we want the following result (i.e., 9ccf1d5 is rebased on top, and the three “Merge branch” commits a0099b7, 932469c and 4bee248 are “squashed” away:
Despite hours of trying various git commands, I’ve been unable to achieve this. |
@billmcspadden-riscv , @rsnikhil I have run all tests of sv32, sv39, and sv48, and the model is passing all tests, so this PR is ready to go. |
else | ||
SAIL_VM_SRCS += $(SAIL_RV64_VM_SRCS) | ||
endif | ||
# SAIL_RV32_VM_SRCS = riscv_vmem_sv32.sail riscv_vmem_rv32.sail |
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The commented out code should be removed. I thought that was fixed in the previous version of this PR?
You know, it would be nice for these long-standing pull requests to give people a heads up when you intend to merge something. An hour between one GitHub user's review (who AFAIK hasn’t got any commits in the repo?) and it being merged is a rather aggressive timeline (and rather lacking in review for something so big and critical), even more so when it’s a public holiday in many countries. |
Hmm - we should probably add something to the contributors notes about that.
…On Mon, Apr 1, 2024 at 8:29 AM Jessica Clarke ***@***.***> wrote:
You know, it would be nice for these long-standing pull requests to give
people a heads up when you intend to merge something. An hour between one
GitHub user (who AFAIK hasn’t got any commits in the repo?) and it being
merged is a rather aggressive timeline (and rather lacking in review for
something so big and critical), even more so when it’s a public holiday in
many countries.
—
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I don't think it was that review that actually prompted the merge (though I may be wrong) but that's a fair point - probably worth a "this will be merged in X days unless anyone has any objections" next time. |
Even more reason to not merge it out of the blue?.. |
We had been discussing merging this for several weeks in our meetings (which are recorded). This was hardly out of the blue. |
Old vmem code had much 'cut-and-paste' replication for RV32 (Sv32) and (riscv#408) RV64 (Sv39, Sv48), and was scattered over several files. New code unifies them into single set of parameterized functions that works for RV32/RV64 and Sv32/Sv39/Sv48 (and is ready for Sv57). Deleted old files: riscv_vmem_rv32.sail riscv_vmem_rv64.sail riscv_vmem_sv32.sail riscv_vmem_sv39.sail riscv_vmem_sv48.sail riscv_pte.sail riscv_ptw.sail Current files: all named riscv_vmem_* riscv_vmem.sail (root file for vmem) riscv_vmem_common.sail riscv_vmem_pte.sail riscv_vmem_ptw.sail riscv_vmem_tlb.sail riscv_vmem_types.sail Modified top-level Makefile accordingly. Added documentation on new vmem code: doc/notes_Virtual_Memory.adoc
Old vmem code had much 'cut-and-paste' replication for RV32 (Sv32) and (riscv#408) RV64 (Sv39, Sv48), and was scattered over several files. New code unifies them into single set of parameterized functions that works for RV32/RV64 and Sv32/Sv39/Sv48 (and is ready for Sv57). Deleted old files: riscv_vmem_rv32.sail riscv_vmem_rv64.sail riscv_vmem_sv32.sail riscv_vmem_sv39.sail riscv_vmem_sv48.sail riscv_pte.sail riscv_ptw.sail Current files: all named riscv_vmem_* riscv_vmem.sail (root file for vmem) riscv_vmem_common.sail riscv_vmem_pte.sail riscv_vmem_ptw.sail riscv_vmem_tlb.sail riscv_vmem_types.sail Modified top-level Makefile accordingly. Added documentation on new vmem code: doc/notes_Virtual_Memory.adoc
[ This PR replaces old PR #365 on same topic, which was closed]
Old vmem code had much 'cut-and-paste' replication for RV32 (Sv32) and RV64 (Sv39, Sv48), and was scattered over several files.
New code unifies them into single set of parameterized functions that works for RV32/RV64 and Sv32/Sv39/Sv48 (and is ready for Sv57).
Deleted old files:
riscv_vmem_rv32.sail riscv_vmem_rv64.sail
riscv_vmem_sv32.sail riscv_vmem_sv39.sail riscv_vmem_sv48.sail
riscv_pte.sail
riscv_ptw.sail
Current files: all named riscv_vmem_*
riscv_vmem.sail (root file for vmem)
riscv_vmem_common.sail
riscv_vmem_pte.sail
riscv_vmem_ptw.sail
riscv_vmem_tlb.sail
riscv_vmem_types.sail
Modified top-level Makefile accordingly.
Added documentation on new vmem code: doc/notes_Virtual_Memory.adoc