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Pmm support #452

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Pmm support #452

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f5a2c5a
adding the mseccfg register
HAMZA-AFZAL404 Feb 14, 2024
64e9925
adding Pointer Masking Extention
HAMZA-AFZAL404 Feb 14, 2024
4c19fad
adding PMM extention for Atmoic Instructions
HAMZA-AFZAL404 Feb 15, 2024
15bc3dd
Added pmm in Vector and Improve overall
HAMZA-AFZAL404 Apr 17, 2024
687b24a
Added pmm Support
HAMZA-AFZAL404 Apr 18, 2024
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2 changes: 1 addition & 1 deletion LICENCE
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ Copyright (c) 2017-2024
Brian Campbell
Chris Casinghino
Christopher Pulte
Codasip, for contributions by Tim Hutt
Codasip, for contributions by Tim Hutt, Martin Berger and Ben Fletcher
dylux
eroom1966
Google LLC, for contributions by its employees
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26 changes: 17 additions & 9 deletions Makefile
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Expand Up @@ -32,6 +32,8 @@ SAIL_DEFAULT_INST += riscv_insts_zbb.sail
SAIL_DEFAULT_INST += riscv_insts_zbc.sail
SAIL_DEFAULT_INST += riscv_insts_zbs.sail

SAIL_DEFAULT_INST += riscv_insts_zcb.sail

SAIL_DEFAULT_INST += riscv_insts_zfh.sail
# Zfa needs to be added after fext, dext and Zfh (as it needs
# definitions from those)
Expand Down Expand Up @@ -71,15 +73,21 @@ SAIL_SYS_SRCS += riscv_softfloat_interface.sail riscv_fdext_regs.sail riscv_fdex
SAIL_SYS_SRCS += riscv_csr_ext.sail # access to CSR extensions
SAIL_SYS_SRCS += riscv_sys_control.sail # general exception handling

SAIL_RV32_VM_SRCS = riscv_vmem_sv32.sail riscv_vmem_rv32.sail
SAIL_RV64_VM_SRCS = riscv_vmem_sv39.sail riscv_vmem_sv48.sail riscv_vmem_rv64.sail

SAIL_VM_SRCS = riscv_pte.sail riscv_ptw.sail riscv_vmem_common.sail riscv_vmem_tlb.sail
ifeq ($(ARCH),RV32)
SAIL_VM_SRCS += $(SAIL_RV32_VM_SRCS)
else
SAIL_VM_SRCS += $(SAIL_RV64_VM_SRCS)
endif
# SAIL_RV32_VM_SRCS = riscv_vmem_sv32.sail riscv_vmem_rv32.sail
# SAIL_RV64_VM_SRCS = riscv_vmem_sv39.sail riscv_vmem_sv48.sail riscv_vmem_rv64.sail

# SAIL_VM_SRCS = riscv_pte.sail riscv_ptw.sail riscv_vmem_common.sail riscv_vmem_tlb.sail
# ifeq ($(ARCH),RV32)
# SAIL_VM_SRCS += $(SAIL_RV32_VM_SRCS)
# else
# SAIL_VM_SRCS += $(SAIL_RV64_VM_SRCS)
# endif

SAIL_VM_SRCS += riscv_vmem_common.sail
SAIL_VM_SRCS += riscv_vmem_pte.sail
SAIL_VM_SRCS += riscv_vmem_ptw.sail
SAIL_VM_SRCS += riscv_vmem_tlb.sail
SAIL_VM_SRCS += riscv_vmem.sail

# Non-instruction sources
PRELUDE = prelude.sail $(SAIL_XLEN) $(SAIL_FLEN) $(SAIL_VLEN) prelude_mem_metadata.sail prelude_mem.sail
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10 changes: 10 additions & 0 deletions c_emulator/riscv_platform.c
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Expand Up @@ -32,6 +32,11 @@ bool sys_enable_fdext(unit u)
return rv_enable_fdext;
}

bool sys_enable_zcb(unit u)
{
return rv_enable_zcb;
}

bool sys_enable_zfinx(unit u)
{
return rv_enable_zfinx;
Expand All @@ -42,6 +47,11 @@ bool sys_enable_writable_fiom(unit u)
return rv_enable_writable_fiom;
}

bool sys_enable_pmm(unit u)
{
return rv_enable_pmm;
}

bool sys_enable_vext(unit u)
{
return rv_enable_vext;
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2 changes: 2 additions & 0 deletions c_emulator/riscv_platform.h
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Expand Up @@ -4,9 +4,11 @@
bool sys_enable_rvc(unit);
bool sys_enable_next(unit);
bool sys_enable_fdext(unit);
bool sys_enable_zcb(unit);
bool sys_enable_zfinx(unit);
bool sys_enable_writable_misa(unit);
bool sys_enable_writable_fiom(unit);
bool sys_enable_pmm(unit);
bool sys_enable_vext(unit);

uint64_t sys_pmp_count(unit);
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2 changes: 2 additions & 0 deletions c_emulator/riscv_platform_impl.c
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Expand Up @@ -6,6 +6,7 @@
uint64_t rv_pmp_count = 0;
uint64_t rv_pmp_grain = 0;

bool rv_enable_zcb = false;
bool rv_enable_zfinx = false;
bool rv_enable_rvc = true;
bool rv_enable_next = false;
Expand All @@ -17,6 +18,7 @@ bool rv_enable_dirty_update = false;
bool rv_enable_misaligned = false;
bool rv_mtval_has_illegal_inst_bits = false;
bool rv_enable_writable_fiom = true;
bool rv_enable_pmm = false;

uint64_t rv_ram_base = UINT64_C(0x80000000);
uint64_t rv_ram_size = UINT64_C(0x4000000);
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2 changes: 2 additions & 0 deletions c_emulator/riscv_platform_impl.h
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Expand Up @@ -11,6 +11,7 @@
extern uint64_t rv_pmp_count;
extern uint64_t rv_pmp_grain;

extern bool rv_enable_zcb;
extern bool rv_enable_zfinx;
extern bool rv_enable_rvc;
extern bool rv_enable_next;
Expand All @@ -21,6 +22,7 @@ extern bool rv_enable_dirty_update;
extern bool rv_enable_misaligned;
extern bool rv_mtval_has_illegal_inst_bits;
extern bool rv_enable_writable_fiom;
extern bool rv_enable_pmm;
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Nit: Here and throughout the PR, pmm is used to refer to pointer masking. I think "pm" or "zpm" would be a better naming (PMM stands for "pointer masking mode", which is only referring to the bits used to configure pointer masking).

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That’s a great suggestion. I will proceed with changing it to "zpm".


extern uint64_t rv_ram_base;
extern uint64_t rv_ram_size;
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18 changes: 15 additions & 3 deletions c_emulator/riscv_sim.c
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Expand Up @@ -53,6 +53,7 @@ const char *RV32ISA = "RV32IMAC";
#define OPT_ENABLE_WRITABLE_FIOM 1001
#define OPT_PMP_COUNT 1002
#define OPT_PMP_GRAIN 1003
#define OPT_ENABLE_ZCB 10014

static bool do_dump_dts = false;
static bool do_show_times = false;
Expand Down Expand Up @@ -135,6 +136,7 @@ static struct option options[] = {
{"report-arch", no_argument, 0, 'a' },
{"test-signature", required_argument, 0, 'T' },
{"signature-granularity", required_argument, 0, 'g' },
{"enable-pmm", no_argument, 0, 'Y' },
#ifdef RVFI_DII
{"rvfi-dii", required_argument, 0, 'r' },
#endif
Expand All @@ -144,7 +146,8 @@ static struct option options[] = {
{"trace-output", required_argument, 0, OPT_TRACE_OUTPUT },
{"inst-limit", required_argument, 0, 'l' },
{"enable-zfinx", no_argument, 0, 'x' },
{"enable-writable-fiom", no_argument, 0, OPT_ENABLE_WRITABLE_FIOM},
{"enable-writable-fiom", no_argument, 0, OPT_ENABLE_WRITABLE_FIOM},
{"enable-zcb", no_argument, 0, OPT_ENABLE_ZCB },
#ifdef SAILCOV
{"sailcov-file", required_argument, 0, 'c' },
#endif
Expand Down Expand Up @@ -261,6 +264,7 @@ static int process_args(int argc, char **argv)
"T:"
"g:"
"h"
"Y"
#ifdef RVFI_DII
"r:"
#endif
Expand Down Expand Up @@ -288,7 +292,7 @@ static int process_args(int argc, char **argv)
break;
case OPT_PMP_COUNT:
pmp_count = atol(optarg);
fprintf(stderr, "PMP count: %lld\n", pmp_count);
fprintf(stderr, "PMP count: %" PRIu64 "\n", pmp_count);
if (pmp_count != 0 && pmp_count != 16 && pmp_count != 64) {
fprintf(stderr, "invalid PMP count: must be 0, 16 or 64");
exit(1);
Expand All @@ -297,7 +301,7 @@ static int process_args(int argc, char **argv)
break;
case OPT_PMP_GRAIN:
pmp_grain = atol(optarg);
fprintf(stderr, "PMP grain: %lld\n", pmp_grain);
fprintf(stderr, "PMP grain: %" PRIu64 "\n", pmp_grain);
if (pmp_grain >= 64) {
fprintf(stderr, "invalid PMP grain: must less than 64");
exit(1);
Expand All @@ -312,6 +316,10 @@ static int process_args(int argc, char **argv)
fprintf(stderr, "enabling N extension.\n");
rv_enable_next = true;
break;
case 'Y':
fprintf(stderr, "enabling pointer masking support.\n");
rv_enable_pmm = true;
break;
case 'I':
fprintf(stderr, "disabling writable misa CSR.\n");
rv_enable_writable_misa = false;
Expand Down Expand Up @@ -386,6 +394,10 @@ static int process_args(int argc, char **argv)
case 'l':
insn_limit = atoi(optarg);
break;
case OPT_ENABLE_ZCB:
fprintf(stderr, "enabling Zcb extension.\n");
rv_enable_zcb = true;
break;
case 'x':
fprintf(stderr, "enabling Zfinx support.\n");
rv_enable_zfinx = true;
Expand Down
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