Use physical addresses for LR/SC reservations #501
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Timmmm
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This changes the behaviour of At first glance the new behaviour seems to match spike: https://github.com/riscv-software-src/riscv-isa-sim/blob/98d2c29e431f3b14feefbda48c5f70c2f451acf2/riscv/mmu.h#L266 |
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I suspect the answer is it's implementation defined what happens. Right now the RISC-V axiomatic memory model in the ISA manual does not specify anything regarding virtual memory. If we do end up with an axiomatic model with virtual memory, we might need something like |
model/riscv_insts_aext.sail
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| * For now we set them on virtual addresses, since it makes the | ||
| * sequential model of SC a bit simpler, at the cost of an explicit | ||
| * call to load_reservation in LR and cancel_reservation in SC. | ||
| * However the reservation is architecturally defined in terms of physical |
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Is this actually the case? The LR and SC section of the unpriv spec never uses the word physical. "a set of bytes that subsumes the bytes in the addressed word." seems intentionally fuzzy to allow a range of implementations.
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OTOH, when I search the priv spec: "For implementations with both page-based virtual memory and the "A" standard extension, the LR/SC
reservation set must lie completely within a single base physical page (i.e., a naturally aligned 4 KiB
physical-memory region)."
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This is based on this comment; maybe the language is a little too strong for something in an second hand email... Maybe I should just remove that comment? Though the quote you found does indirectly support it.
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Ok comment removed.
This is how reservation is architecturally defined, how real CPUs are likely to be implemented, and doesn't require spurious cancellations on xRET and traps. Fixes riscv#360.
Timmmm
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@billmcspadden-riscv ok this is ready now. |
This is how reservation is architecturally defined, how real CPUs are likely to be implemented, and doesn't require spurious cancellations on xRET and traps.
Fixes #360.