DKOP

This repository contains all the Verilog and System Verilog codes made during training at DKOP.

Name		Name	Last commit message	Last commit date
Latest commit History 66 Commits
Booth_Multiplier2		Booth_Multiplier2
System Verilog		System Verilog
alu_4op		alu_4op
b2g		b2g
booth_multiplier		booth_multiplier
buffer		buffer
cases		cases
comparator_nbit		comparator_nbit
counters		counters
decoder3to8		decoder3to8
decoder4to10		decoder4to10
decoder_nbit		decoder_nbit
encoder8to3		encoder8to3
fork_join		fork_join
full_using_half		full_using_half
fulladder		fulladder
fullsubtractor		fullsubtractor
g2b		g2b
halfadder		halfadder
halfsubtractor		halfsubtractor
mul_2bit		mul_2bit
mux2to1		mux2to1
mux4to1		mux4to1
mux_nbit		mux_nbit
parity_chck_gen		parity_chck_gen
shifts		shifts
sq_3bit		sq_3bit
srlatch		srlatch
swap		swap
test		test
test_real		test_real
triregtest		triregtest
vedic_mul		vedic_mul
README.md		README.md

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