Table of Contents

Serial No.	Name	Description	Vivado and HLS Version	Board
1	Simple Arithmetic Calculation	Fixed point data transfer using AXI Lite interface	2019.1	PYNQ Z2
2	Matrix Multiplication	Floating point data transfer using AXI Stream interface	2019.1	PYNQ Z2
3	Simple Arithmetic Calculation	Fixed point data transfer using AXI Lite interface	2022.1	RFSoC4x2
4	Matrix Multiplication	Floating point data transfer using AXI Stream interface	2022.1	PYNQ Z2
5	Addition 1 (Add 5 to Input)	Fixed point data transfer using AXI Stream interface	2022.1	PYNQ Z2
6	Addition 1 (Add 5 to Input)	Fixed point data transfer using AXI Stream interface	2022.1	RFSoC4x2
7	Simple Arithmetic Calculation	Floating point data transfer using AXI Lite interface	2022.1	RFSoC4x2
8	Matrix Multiplication	Floating point data transfer using AXI Stream interface	2022.1	RFSoC4x2
9	Addition 2 (Add 2 Numbers)	Floating point data transfer using AXI Stream interface	2022.1	RFSoC4x2
10	Addition 3 (Add 0.5 to Input)	Floating point data transfer using AXI Stream interface	2022.1	RFSoC4x2
11	Aggregation	Using aggregate pragma	2022.1	RFSoC4x2

Sources

Algorithms to Architure Lab IIITD

HLS Stream IP with DMA Tutorial

PYNQ Documentation

Using DMA with PYNQ

Floating Point Data Transfer using AXI Stream Interface

Aggregate Pragma Examples

Aggregate Pragma Documentation