librz/arch: capstone v6 update (without MIPS) (#4662)

* Bumps Capstone version to newest Capstone next (beyond first v6-Alpha1). * Fixes leaks * Fixes build and change to AArch64 and SystemZ compatibility headers. * Marks M68k test as broken (see commit message). * Fix AArch64 and SystemZ tests * Handle op.size == 0 for x86 IL ops
rizinorg · Oct 24, 2024 · f82993a · f82993a
1 parent 2fafb3d
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diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -160,6 +160,16 @@ jobs:
             timeout: 45
             cflags: "-Wno-cpp"
             allow_failure: true
+          - name: capstone-v6
+            os: ubuntu-22.04
+            build_system: meson
+            compiler: gcc
+            meson_options: -Dbuildtype=release -Duse_capstone_version=v6 --werror
+            run_tests: false
+            enabled: ${{ (github.event_name != 'pull_request' || contains(github.head_ref, 'capstone')) && needs.changes.outputs.edited == 'true' }}
+            timeout: 45
+            cflags: "-Wno-cpp"
+            allow_failure: false
           - name: no-gpl-code
             os: ubuntu-22.04
             build_system: meson

diff --git a/doc/PACKAGERS.md b/doc/PACKAGERS.md
@@ -66,7 +66,7 @@ version of Capstone be dynamically linked at runtime. To do this, use the
 `-Duse_sys_capstone=enabled` command line option when running `meson`.
 
 You can override the version of Capstone Rizin will use by setting
-`use_capstone_version` to one of `v4`, `v5` or `next`.
+`use_capstone_version` to one of `v4`, `v5`, `v6` or `next`.
 
 There are more bundled dependencies that can be swapped out for system versions.
 At the time of writing, these are:

diff --git a/librz/arch/isa/arm/aarch64_meta_macros.h b/librz/arch/isa/arm/aarch64_meta_macros.h
diff --git a/librz/arch/isa/arm/arm_accessors32.h b/librz/arch/isa/arm/arm_accessors32.h
@@ -7,6 +7,9 @@
  *     cs_insn *insn
  */
 
+#pragma GCC diagnostic ignored "-Wenum-compare"
+#pragma GCC diagnostic ignored "-Wenum-conversion"
+#define CAPSTONE_AARCH64_COMPAT_HEADER
 #include <capstone/capstone.h>
 
 #define REGID(x)   insn->detail->arm.operands[x].reg
@@ -27,14 +30,24 @@
 #define ISMEM(x)   (insn->detail->arm.operands[x].type == ARM_OP_MEM)
 #define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP)
 
-#define LSHIFT(x)       insn->detail->arm.operands[x].mem.lshift
-#define LSHIFT2(x)      insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL
-#define OPCOUNT()       insn->detail->arm.op_count
-#define ISSHIFTED(x)    (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0)
-#define SHIFTTYPE(x)    insn->detail->arm.operands[x].shift.type
+#if CS_NEXT_VERSION < 6
+#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift
+#else
+#define LSHIFT(x) insn->detail->arm.operands[x].shift.value
+#endif
+#define LSHIFT2(x)   insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL
+#define OPCOUNT()    insn->detail->arm.op_count
+#define ISSHIFTED(x) (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0)
+#define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type
+
+#if CS_NEXT_VERSION < 6
 #define SHIFTTYPEREG(x) (SHIFTTYPE(x) == ARM_SFT_ASR_REG || SHIFTTYPE(x) == ARM_SFT_LSL_REG || \
 	SHIFTTYPE(x) == ARM_SFT_LSR_REG || SHIFTTYPE(x) == ARM_SFT_ROR_REG || \
 	SHIFTTYPE(x) == ARM_SFT_RRX_REG)
+#else
+#define SHIFTTYPEREG(x) (SHIFTTYPE(x) == ARM_SFT_ASR_REG || SHIFTTYPE(x) == ARM_SFT_LSL_REG || \
+	SHIFTTYPE(x) == ARM_SFT_LSR_REG || SHIFTTYPE(x) == ARM_SFT_ROR_REG)
+#endif
 #define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value
 
 #if CS_NEXT_VERSION >= 6

diff --git a/librz/arch/isa/arm/arm_accessors64.h b/librz/arch/isa/arm/arm_accessors64.h
@@ -7,22 +7,23 @@
  *     cs_insn *insn
  */
 
+#define CAPSTONE_AARCH64_COMPAT_HEADER
 #include <capstone/capstone.h>
 
-#define IMM64(x)   (ut64)(insn->detail->CS_aarch64_.operands[x].imm)
-#define INSOP64(x) insn->detail->CS_aarch64_.operands[x]
+#define IMM64(x)   (ut64)(insn->detail->arm64.operands[x].imm)
+#define INSOP64(x) insn->detail->arm64.operands[x]
 
-#define REGID64(x)   insn->detail->CS_aarch64_.operands[x].reg
-#define REGBASE64(x) insn->detail->CS_aarch64_.operands[x].mem.base
+#define REGID64(x)   insn->detail->arm64.operands[x].reg
+#define REGBASE64(x) insn->detail->arm64.operands[x].mem.base
 // s/index/base|reg/
-#define HASMEMINDEX64(x) (insn->detail->CS_aarch64_.operands[x].mem.index != CS_AARCH64(_REG_INVALID))
-#define MEMDISP64(x)     (ut64) insn->detail->CS_aarch64_.operands[x].mem.disp
-#define ISIMM64(x)       (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_IMM))
-#define ISREG64(x)       (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_REG))
-#define ISMEM64(x)       (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_MEM))
+#define HASMEMINDEX64(x) (insn->detail->arm64.operands[x].mem.index != ARM64_REG_INVALID)
+#define MEMDISP64(x)     (ut64) insn->detail->arm64.operands[x].mem.disp
+#define ISIMM64(x)       (insn->detail->arm64.operands[x].type == ARM64_OP_IMM)
+#define ISREG64(x)       (insn->detail->arm64.operands[x].type == ARM64_OP_REG)
+#define ISMEM64(x)       (insn->detail->arm64.operands[x].type == ARM64_OP_MEM)
 
-#define LSHIFT2_64(x) insn->detail->CS_aarch64_.operands[x].shift.value
-#define OPCOUNT64()   insn->detail->CS_aarch64_.op_count
+#define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value
+#define OPCOUNT64()   insn->detail->arm64.op_count
 
 #if CS_NEXT_VERSION < 6
 #define ISWRITEBACK64() (insn->detail->arm64.writeback == true)
@@ -33,6 +34,6 @@
 #define ISPREINDEX64()  (((OPCOUNT64() == 2) && (ISMEM64(1)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 3) && (ISMEM64(2)) && (ISWRITEBACK64())))
 #define ISPOSTINDEX64() (((OPCOUNT64() == 3) && (ISIMM64(2)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 4) && (ISIMM64(3)) && (ISWRITEBACK64())))
 #else
-#define ISPREINDEX64()  (!insn->detail->CS_aarch64_.post_index && ISWRITEBACK64())
-#define ISPOSTINDEX64() (insn->detail->CS_aarch64_.post_index && ISWRITEBACK64())
-#endif
+#define ISPREINDEX64()  (!insn->detail->arm64.post_index && ISWRITEBACK64())
+#define ISPOSTINDEX64() (insn->detail->arm64.post_index && ISWRITEBACK64())
+#endif
diff --git a/librz/arch/isa/arm/arm_cs.h b/librz/arch/isa/arm/arm_cs.h
@@ -5,8 +5,10 @@
 #define RZ_ARM_CS_H
 
 #include <rz_analysis.h>
+#pragma GCC diagnostic ignored "-Wenum-compare"
+#pragma GCC diagnostic ignored "-Wenum-conversion"
+#define CAPSTONE_AARCH64_COMPAT_HEADER
 #include <capstone/capstone.h>
-#include "aarch64_meta_macros.h"
 
 RZ_IPI int rz_arm_cs_analysis_op_32_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn, bool thumb);
 RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn);
@@ -19,7 +21,7 @@ RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCode
 #else
 RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type);
 #endif
-RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, CS_aarch64_cc() cond_type);
+RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, ARM64CC_CondCode cond_type);
 
 RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb);
 RZ_IPI RzAnalysisILConfig *rz_arm_cs_32_il_config(bool big_endian);

diff --git a/librz/arch/isa/arm/arm_esil32.c b/librz/arch/isa/arm/arm_esil32.c
@@ -2,6 +2,9 @@
 // SPDX-License-Identifier: LGPL-3.0-only
 
 #include <rz_analysis.h>
+#pragma GCC diagnostic ignored "-Wenum-compare"
+#pragma GCC diagnostic ignored "-Wenum-conversion"
+#define CAPSTONE_AARCH64_COMPAT_HEADER
 #include <capstone/capstone.h>
 
 #include "arm_cs.h"
@@ -34,7 +37,9 @@ static const char *decode_shift(arm_shifter shift) {
 	case ARM_SFT_ROR:
 	case ARM_SFT_RRX:
 	case ARM_SFT_ROR_REG:
+#if CS_NEXT_VERSION < 6
 	case ARM_SFT_RRX_REG:
+#endif
 		return E_OP_RR;
 
 	default: