- VDD - 1.8 to 5.5V
- GND
- DELAY (DLY) - Time Interval set and Manual Reset
- DONE - Logic Input for watchdog functionality
- WAKE - Timer output signal generated every Digital pulsed signal to wake up the µC at the end of tIP period.
- RST - Reset Output (open drain output)
- Add TPL5010
- Add resistor for 100MS
- Add resistor for 500MS
- Add resistor for 1S
- Add resistor for 3S
- Add resistor for 5S